Due-date based scheduling and control policies in a multiproductsemiconductor wafer fabrication facility

This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of processing waiting lots in front of workstations for lot scheduling. New dispatching rules are developed for lot release control and scheduling considering special features of the wafer fabrication process. Simulation experiments are carried out to test the dispatching rules. Results show that lot release control and lot scheduling at photolithography workstations are more important than scheduling at other workstations. Also, it is shown that new dispatching rules work better in terms of tardiness of orders than existing rules such as the EDD (earliest due date) rule and other well-known dispatching rules for multimachine scheduling     

Scheduling of semiconductor test facility via Petri nets and hybridheuristic search

This paper proposes and evaluates two Petri net-based hybrid heuristic search strategies and their applications to semiconductor test facility scheduling. To reduce the setup time, such as the time spent to bring the test facilities to the required temperatures, scheduling multiple lots for each job type together is desirable. Petri nets can concisely model multiple lot sizes for each job, the strict precedence constraints, multiple kinds of resources, concurrent activities and flexible routes. To cope with the complexities for multiple lots scheduling, this paper presents two Petri net-based hybrid heuristic search strategies. They combine the heuristic best-first strategy with the controlled back tracking strategy based on the execution of the Petri nets. The obtained scheduling results are compared and analyzed through a small-size test facility. The better algorithm is also applied to a more sizable facility containing types of resources with a total of 79 pieces and 30 jobs. The future work includes the real-time implementation of the proposed method and scheduling results in real industrial settings     

Characterization of operational time variability using effective process times

Operational time variability is one of the key parameters determining the average cycle time of lots. Many different sources of variability can be identified such as machine breakdowns, setup, and operator availability. However, an appropriate measure to quantify variability is missing. Measures such as overall equipment effectiveness (OEE) used in the semiconductor industry are entirely based on mean value analysis and do not include variances. The main contribution of this paper is the development of a new algorithm that enables estimation of the mean effective process time t/sub e/ and the coefficient of variation c/sub e//sup 2/ of a multiple machine workstation from real fab data. The algorithm formalizes the effective process time definitions as known in the literature. The algorithm quantifies the claims of machine capacity by lots, which include time losses due to down time, setup time, and other irregularities. The estimated t/sub e/ and c/sub e//sup 2/ values can be interpreted in accordance with the well-known G/G/m queueing relations. Some test examples as well as an elaborate case from the semiconductor industry show the potential of the new effective process time algorithm for cycle time reduction programs.     

An improved methodology for real-time production decisions atbatch-process work stations

Demonstrates a methodology which uses the information of future work-in-process (WIP) arrivals to minimize the average number of lots in the queue at a workstation which is capable of processing multiple lots simultaneously as a single batch. This kind of batch-process workstation is common in semiconductor manufacturing; an example is furnace tubes used for deposition operations. The proposed heuristic seeks to minimize the average number of lots waiting in the queue by choosing start times for process cycles that minimize the total lot queue time per unit time over a scheduling horizon equal to the processing time plus any prior waiting time     

A combined fuzzy-logic and physics-of-failure approach toreliability prediction

An original reliability prediction procedure is presented. The physics of failure accounts for the failure mechanisms involved (a lognormal distribution was presumed); the interactions (synergies) between the technology factors depending on the manufacturing techniques are considered. The basis of this methodology (called SYRP=synergetic reliability prediction) is the assessment of failure-risk coefficients (FRC), based on fuzzy logic, for the potential failure mechanisms induced at each manufacturing step. These FRC are corrected at the subsequent steps by considering the synergy of the manufacturing factors, At the end of the manufacturing process, final FRC are obtained for each potential failure mechanism; the parameters of the lognormal distribution are calculated with a simple algorithm. Experimental results for four lots of the same type of semiconductor devices, each lot being manufactured with a slightly different technology, were obtained. SYRP forecasts for these four lots agree well with accelerated life test results. This is a fairly good result, because SYRP was used early, at the design phase     

A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility

This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy.      

Neural-network-based delivery time estimates for prioritized 300-mm automatic material handling operations

This paper deals with lot delivery estimates in a 300-mm automatic material handling system (AMHS), which is composed of several intrabay loops. We adopt a neural network approach to estimate the delivery times for both priority and regular lots. A network model is developed for each intrabay loop. Inputs to the proposed neural network model are the combination of transport requirements, automatic material handling resources, and ratios of priority lots against regular ones. A discrete-event simulation model based on the AMHS in a local 300-mm fab is built. Its outputs are adopted for training the neural network model with the back propagation method. The outputs of the neural network model are the expected delivery times of priority and regular lots in the loop, respectively. For a lot to be transported, its expected delivery time along a potential delivery path is estimated by the summation of all the loop delivery times along the path. A shortest path algorithm is used to find the path with the shortest delivery time among all the possible delivery paths. Numerical experiments based on realistic data from a 300-mm fab indicate that this neural network approach is sound and effective for the prediction of average delivery times. Both the delivery times for priority and regular lots get improved. Specially, for the cases of regular lots, our approach dynamically routes the lots according to the traffic conditions so that the potential blockings in busy loops can be avoided. This neural network approach is applicable to implementing a transport time estimator in dynamic lot dispatching and fab scheduling functions in realizing fully automated 300-mm manufacturing.     

带等待时间约束并行机调度问题的Copula分布估计算法

本文针对一类带等待时间约束的不相关并行机调度问题,提出了一种基于Copula函数的分布估计算法.该算法以同类订单工件数与总工件数的比值为变量,对每台机器构造了一个Copula函数,进而建立了优势种群的概率模型.基于概率模型通过采样生成子代个体编码向量组,保留了父代种群的相对位置信息.从理论上分析了所提出算法的时间复杂度,其随工件个数的增加呈对数增长.通过基于实例的数值仿真以及与已有算法的比较验证了所提算法的有效性和鲁棒性.     

Scrapping small lots in a low-yield and high-price scenario

Some wafers in a lot may become spoiled after they are processed at a workstation; such a lot is called a small lot. In a low yield and high price scenario, scrapping small lots may increase revenue and profit; yet, this notion has seldom been examined. This study presents a model for formulating the decision-making problem of scrapping small lots. A genetic algorithm is used to solve the problem when the solution space is large. An exhaustive search method is used when the solution space is small. Some numerical examples are used to evaluate the outcome of scrapping small lots. The profit obtained by the proposed scrapping method may be up to 23% higher than that obtained without scrapping.     

Factory cycle-time prediction with a data-mining approach

An estimate of cycle time for a product in a factory is critical to semiconductor manufacturers (and in other industries) to assess customer due dates, schedule resources and actions for anticipated job completions, and to monitor the operation. Historical data can be used to learn a predictive model for cycle time based on measured and calculated process metrics (such as work-in-progress at specific operations, lot priority, product type, and so forth). Such a method is relatively easy to develop and maintain. Modern data mining algorithms are used to develop nonlinear predictors applicable to the majority of process lots, and three methods are compared here. They are compared with respect to performance in actual manufacturing data (to predict times for both final and intermediate steps) and for the feasibility to maintain and rebuild the model.     

Metaheuristic scheduling of 300-mm lots containing multiple orders

The standard unit of transfer in new semiconductor wafer fabrication facilities is the front opening unified pod (FOUP). Due to automated material handling system concerns, the number of FOUPs in a wafer fab is kept limited. Moreover, a certain number of new and larger 300-mm wafers will be placed in these FOUPs and this makes grouping orders from multiple customers into a job a necessity. Thereby, efficient utilization of the FOUP capacity while attaining good system performance is a challenge. We previously investigated optimization-based solution approaches for minimizing total weighted completion time and maximizing on-time delivery performance for the single machine multiple orders per job scheduling problem. We present two metaheuristic solution approaches for this scheduling problem under two different typical wafer fab machine environments: single unit processing and single lot processing. Experimental results demonstrate that the metaheuristic approaches can find near-optimal solutions for realistic-sized 300-mm scheduling problems in an acceptable amount of computation time.     

Modeling the effect of hot lots in semiconductor manufacturingsystems

The presence of hot lots or high-priority jobs in semiconductor manufacturing systems is known to significantly affect the cycle time and throughput of the regular lots since the hot lots get priority at all stages of processing. In this paper, we present an efficient analytical model based on re-entrant lines and use an efficient, approximate analysis methodology for this model in order to predict the performance of a semiconductor manufacturing line in the presence of hot lots. The proposed method explicitly models scheduling policies and can be used for rapid performance analysis. Using the analytical method and also simulation, we analyze two re-entrant lines, including a full-scale model of a wafer fab, under various buffer priority scheduling policies. The numerical results show the severe effects hot lots can have on the performance characteristics of regular lots     

Quick-turnaround-time improvement for product development andtransfer to mass production

We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot management is introduced to keep the optimum balance of manufacturing TAT and throughput. Substantial end-user computing reduces the engineering holding time for handling development lots. In situ monitoring technologies are applied for the utilization enhancement of plasma-assisted equipment. A 9% manufacturing TAT reduction and a 14% throughput increase are estimated using a manufacturing simulator. The number of wafers in QTAT lots is reduced for processing time reduction. As a result, manufacturing TAT of QTAT lots with reduction from 24 wafers to three is reduced to 56% compared with that of normal lots in the production fab. This new production fab realizes QTAT development and agile product transfer from development to mass production with full process compatibility     

A Multiagent-Based Decision-Making System for Semiconductor Wafer Fabrication With Hard Temporal Constraints

This paper presents a decision-making system for semiconductor wafer fabrication facilities, or wafer fabs, with hard interoperation temporal constraints. The decision-making system is developed based on a multiagent architecture that is composed of scheduling agents, workcell agents, machine agents, and product agents. The decision-making problem is to allocate lots into each workcell to satisfy both logical and temporal constraints. A dynamic planning-based approach is adopted for the decision-making mechanism so that the dynamic behaviors of the wafer fab such as aperiodic lot arrivals and reconfiguration can be taken into consideration. The scheduling agents compute quasi-optimal schedules through a bidding mechanism with the workcell agents. The proposed decision-making mechanism uses a concept of temporal constraint sets to obtain a feasible schedule in polynomial steps. The computational complexity of the decision-making mechanism is proven to be, where is the number of operations of a lot and is the cardinality of the temporal constraint set.     

基于随机投影深度函数的停车场车辆提取方法

为精确提取露天停车场内颜色混杂的车辆，提出一种基于随机投影深度函数的车辆提取方法.随机投影深度函数可有效区分RGB彩色空间中数据集的数据中心与离群值，充分利用各车辆颜色特征的复杂性及其与停车场背景颜色特征的差异性，凸显具有离群值颜色特征的车辆.首先，利用随机投影深度函数对彩色遥感影像中各像素颜色特征进行排序得到深度场影像；然后，对深度场影像做形态学闭运算并选取合适的随机投影深度值作为阈值，二值化闭运算后的深度场影像，实现车辆初始提取；最后，结合决策树分析与形态学运算实现车辆精确提取.实验结果表明，随机投影深度函数可有效处理彩色遥感影像中各种颜色车辆所表现的"同物异谱"现象，在深度场影像中凸显不同颜色的车辆，有效提高车辆提取效率；辅助以简单的后处理可实现遥感影像中不同场景停车场车辆提取.     

基于Petri网与遗传算法的半导体生产线建模与优化调度

针对半导体生产线调度复杂、难以优化的问题,本文提出了一种基于层次有色赋时Petri网技术和遗传算法相结合的优化调度方法。该方法利用层次化的方法结合自顶向下建模方法对半导体生产线进行模块化建模,模型不仅能够反映生产线的待加工产品的多条加工路径及其资源约束,还可以对系统的设备维护、各种优先级等特性进行描述,得到对生产系统更完善更精确的刻画。通过在遗传算法编码中同时考虑投料策略、工件选设备规则、批加工调度规则和单件加工设备规则等因素得到更加有效的调度方案,提高了模型的优化程度。在此基础上,对实际半导体生产线的不同调度方案分别进行了仿真,并对仿真结果进行了比较,从而验证了建模方法的正确性及调度策略的有效性。     

Quantifying variability of batching equipment using effective process times

Process time variability plays a key role in the cycle time of wafers. Several sources of variability can be distinguished. However, identification and measurement of all individual sources is almost impossible. Therefore, in previous work, a new method has been proposed to measure effective process times (EPT) for single-lot machines. The EPT incorporates the various sources of variability. From the measured EPT realizations, the mean and the corresponding coefficient of variation can be computed for queueing performance analysis. This paper follows up on previous work. The EPT quantification approach is generalized toward batching equipment. The batching types of operations are commonly present in the semiconductor industry. The paper proposes a transformation algorithm that transforms lot events into batch events. This enables one to use the previously developed single-lot algorithm also for batch machine workstations. An industry case illustrates the approach using operational data of furnace workstations.     

对基于图像分割与合并的相位展开算法的改进

为了提高基于图像分割与合并的相位展开算法的精度,对已有的一种算法进行多方面改进,采取区域不等分措施,使得区域信息完整、准确再现;针对不同区域的噪声及欠采样情况,分别采取不同的相位展开算法;对分块合并时重叠区域进行加权叠加处理。利用仿真和实测数据对算法进行了验证,结果表明,改进算法能更准确、快速地恢复出被测物体的相位信息。改进后的算法不但适合于超大规模图像的相位展开,也适合于部分区域条纹过密的包裹相位图的展开。     

Daily scheduling for R&D semiconductor fabrication

This paper presents the development of a daily scheduling tool, Electronic Research and Service Organization Fab Scheduler (ERSOFS), for a research and development (R&D) pilot line of semiconductor wafer fabrication. An integer programming problem formulation is first given, which captures the salient features such as high variety and very low volume, cyclic process flows, batching at diffusion machines, single mask for each photolithography operation, loop test and engineering splitting and merging of wafer lots. A solution methodology based on Chang and Liao's approach [1994] for scheduling flexible flow shops is then extended to this class of problems. The solution methodology is implemented and validated in an R&D fab. Results indicate that ERSOFS efficiently generates schedules of high quality. The rescheduling function of ERSOFS provides fast and smooth adjustments of schedules to cope with the. high production uncertainties in an R&D fab. Analysis of the algorithmic properties demonstrates the potential of ERSOFS for application to larger fabs     

A queueing network model for semiconductor manufacturing

We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost