一种可重构体系结构用于高速实现DES、3DES和AES

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景.然而目前的可重构密码芯片吞吐率均大大低于专用芯片,因此,如何提高处理速度是可重构密码芯片设计的关键问题.本文分析了常用对称密码算法DES、3DES和AES的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构.基于该体系结构实现的DES、3DES和AES吞吐率在110MHz工作频率下分别可达到7Gbps、2.3Gbps和1.4Gbps.与其他同类设计相比,本文设计在处理速度上有较大优势,可以很好地应用到可重构密码芯片设计中.     

可重构分组密码指令集处理器自动映射方法研究

计算资源与寄存器资源分配是可重构处理器自动并行映射的重要问题,该文针对可重构分组密码指令集处理器的资源分配问题,建立算子调度参数模型和处理器资源参数模型,研究了分组密码并行调度与资源消耗之间的约束关系;在此基础上提出基于贪婪思维、列表调度和线性扫描的自动映射算法,实现了分组密码在可重构分组密码指令集处理器上的自动映射。通过可用资源变化实验验证算法并行映射的有效性,并对AES-128算法的映射效果做了横向对比验证算法的先进性,所提自动映射算法对分组密码在可重构处理中的并行计算研究有一定的指导意义。     

一种面向序列密码的混合粒度并行运算单元

针对可重构密码处理器对于不同域上的序列密码算法兼容性差、实现性能低的问题,该文分析了序列密码算法的多级并行性并提出了一种反馈移位寄存器(FSR)的预抽取更新模型。进而基于该模型设计了面向密码阵列架构的可重构反馈移位寄存器运算单元(RFAU),兼容不同有限域上序列密码算法的同时,采取并行抽取和流水处理策略开发了序列密码算法的反馈移位寄存器级并行性,从而有效提升了粗粒度可重构阵列(CGRA)平台上序列密码算法的处理性能。实验结果表明与其他可重构处理器相比,对于有限域(GF)(2)上的序列密码算法,RFAU带来的性能提升为23%～186%;对于GF(2u)域上的序列密码算法,性能提升达约66%～79%,且面积效率提升约64%～91%。     

一种基于流处理框架的可重构分簇式分组密码处理结构模型

可重构密码处理结构是一种面向信息安全处理的新型体系结构,但具有吞吐量和利用率不足的问题。该文提出一种基于流处理框架的阵列结构可重构分组密码处理模型(Stream based Reconfigurable Clustered block Cipher Processing Array, S-RCCPA)。针对分组密码算法特点,采用粗粒度可重构功能单元、基于Crossbar的分级互连网络、分布式密钥池存储结构以及静态与动态相结合的重构方式,支持密码处理路径的动态重组,以不同并行度的虚拟流水线执行密码任务。对典型分组密码算法的适配结果表明,在 CMOS工艺下,依据所适配算法结构的不同,规模为41的S-RCCPA模型的典型分组密码处理性能可达其它架构的5.28~47.84倍。     

PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题,该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征,基于可重构阵列结构设计方法,提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能,该文结合密码算法映射结果,确定模型参数,构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证,芯片面积为12.25mm²,同时,针对该阵列芯片进行密码算法映射.实验结果表明,该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射,在密文分组链接（CBC）模式下,相较于可重构密码逻辑阵列REMUS_LPP结构,其单位面积性能提升了约12.9%,单位功耗性能提升了约13.9%.     

On Random Pattern Testability of Cryptographic VLSI Cores

In this paper we show, that the statistical properties of cryptographic algorithms are the reason for the excellent pseudorandom testability of cryptographic processor cores. The work is especially concerned with modern symmetric block encryption algorithms and their VLSI implementations. For the examination typical basic operations of these cryptographic algorithms are categorized in classes and analyzed regarding their pseudorandom properties. Based on the results the pseudorandom properties of symmetric block ciphers can be determined by means of data flow graphs (DFG) and so-called predecessor operation lists. This is demonstrated with a paradigm algorithm, the symmetric block cipher 3WAY. The results of the theoretical analysis lead to a so-called global BIST concept for cryptographic processor cores. This self-test approach is characterized by central pseudorandom pattern generators and signature registers at the primary inputs and outputs of the cores. The global BIST is exemplarily applied to an implementation of the 3WAY algorithm. Finally, the quality of the developed test approach is determined by fault simulations.     

High-Throughput Area-Efficient Processor for Cryptography

Cryptography circuits for portable elec-tronic devices provide user authentication and secure data communication. These circuits should, achieve high per-formance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a high-performance ASIP (Application specific instruction set processor) for five standard cryptographic algorithms in-cluding both block ciphers (AES, Camellia, and ARIA) and stream ciphers (ZUC and SNOW 3G). The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2 (65 nm). Compared with state-of-the-art VLSI designs, our design achieves high perfor-mance, low silicon cost, low power consumption, and suf-ficient programmability. For its programmability, our de-sign can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.     

Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism

As technology scaling reduces pace and energy efficiency becomes a new important design constraint, superscalar processor designs are reaching their performance limits due to area and power restrictions. As a result, new microarchitectural paradigms need to be developed. This work proposes a new organization for x86 processors, based on a traditional superscalar design coupled to a reconfigurable array. The system exploits the fact that few basic blocks are responsible for most of the instructions that execute in the processor, and transforms these basic blocks into configurations for the reconfigurable array. Each configuration encodes the semantics and dependencies for all instructions in the block, so that the ones already mapped can execute bypassing the fetch, decode and dependency checks stages and improving instruction throughput. Our study on the potential of the architecture shows that performance gains of up to 2.5\(\times \) with respect to a traditional superscalar can be achieved.     

柔性结构的AES加密芯片设计

提出了基于有限域运算单元的柔性AES加密系统。通过对不同密钥扩展的算法进行比较分析,利用其基本运算单元相同的特性,采用控制单元实现可支持128位、192位和256位三种密钥长度的柔性结构。采用集成化的可重构柔性AES加密系统,可以降低硬件逻辑资源消耗。使用Verilog HDL硬件语言进行仿真,并在0.35μm工艺下进行逻辑综合。结果表明,时钟频率可达180 MHz,对于128位密钥长度,系统吞吐量可达2.11 Gbps。     

基于流体系结构的高效能分组密码处理器研究

针对现有密码处理器存在的问题,借鉴流处理器架构,提出了高效能的可重构分组密码流处理器架构.该架构采用层次化设计思想,通过分块式本地寄存器组的数据组织方式和共享拼接使用运算单元机制,实现了软件流水和硬件流水的协同工作,能够挖掘分组内和分组间的指令级并行性并提高功能单元的利用率.在65nm CMOS工艺下对架构进行了综合仿真,并经过了大量算法映射.实验结果证明,该架构在CBC和ECB加密模式下均具有良好的加密性能.与其他密码处理器相比,该架构具有小面积、高效能的特点.     

Distributed Spectrum Sensing Using Low Cost Hardware

Lattice Reduction aided MIMO detectors have been demonstrated to offer a promising gain by providing near-optimal performance. This paper presents a C-programmable ASIP baseband processor, for near-optimal MIMO detection targeting a 4×4 LTE system. The detector supports multiple MIMO detection modes, with both hard and soft output. In order to improve implementation efficiency, the previously reported MIMO detection algorithm Multi-Tree Selective Spanning Detector (MTSS) is modified to use orthogonal real-valued decomposition (ORVD). Afterwards, a low-complexity log-likelihood-ratio (LLR) improvement technique called counter-ML bit-flipping algorithm is proposed. The proposed LLR generation algorithm has been designed to take advantage of MTSS, by maximizing the reuse of computations. Performance of the proposed solution can be tuned ranging from SIC to near-ML to near-MAP. The baseband processor is designed using 40 nm process technology with an equivalent gate-count (GE) of 68.41 kGE. Operating at 600 MHz for a 4×4 QAM-64 LTE system, the processor delivers peak-throughputs of 3.6 Gbps and 2.05 Gbps in case of hard and soft output MIMO detection, with 13.03 mW and 22.99 mW respective power consumption. The corresponding energy efficiency is 3.61 pJ/bit and 11.17 pJ/bit. In terms of energy efficiency, the proposed reconfigurable solution is comparable to recently reported ASIC MIMO detectors, while providing multiple-modes of operation and the flexilibility of C-programming.     

星地高速数传系统低复杂度可重构LDPC编码器设计

为满足近地轨道(LEO)卫星星地高速数传系统对高通量、低复杂度、高可靠性信道编码的应用需求,该文提出一种基于国际空间数据系统咨询委员会(CCSDS)近地卫星通信标准低密度奇偶校验(LDPC)码的低复杂度可重构编码器设计实现方案。通过对输入信息比特插0处理和拆分循环矩阵,并分析不同并行度编码的结构特点,实现了可重构编码方案,提高了编码器的灵活性和编码数据吞吐率;采用优化的移位寄存器累加单元,降低了编码器的整体硬件资源规模。在Xilinx FPGA上对提出的编码器进行了实现,结果表明,在125 MHz系统工作时钟下,编码数据吞吐率最高可达1 Gbps,归一化编码数据吞吐率与其它文献并行度相近的编码器相比提高了17.1%,其寄存器资源和查找表资源与相同平台已有方案相比分别降低了13.7%和14.8%。     

VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000

In this paper, we proposed a new architecture of lifting processor for JPEG2000 and implemented it with both FPGA and ASIC. It includes a new cell structure that executes a unit of lifting calculation to satisfy the requirements of the lifting process of a repetitive arithmetic. After analyzing the operational sequence of lifting arithmetic in detail and imposing the causality to implement in hardware, the unit cell was optimized. A new simple lifting kernel was organized by repeatedly arranging the unit cells and a lifting processor was realized for Motion JPEG2000 with the kernel. The proposed processor can handle any size of tiles and support both lossy and lossless operation with (9,7) filter and (5,3) filter, respectively. Also, it has the same throughput rate as the input, and can continuously output the wavelet coefficients of the four types (LL, LH, HL, HH) simultaneously. The lifting processor was implemented in a 0.35 mum CMOS fabrication process, the result of which occupied about 90 000 gates, and was stably operated in about 150 MHz     

粗粒度可重构密码逻辑阵列智能映射算法研究

针对粗粒度可重构密码逻辑阵列密码算法映射周期长且性能不高的问题,该文通过构建粗粒度可重构密码逻辑阵列参数化模型,以密码算法映射时间及实现性能为目标,结合本文构建的粗粒度可重构密码逻辑阵列结构特征,提出了一种算法数据流图划分算法.通过将密码算法数据流图中节点聚集成簇并以簇为最小映射粒度进行映射,降低算法映射复杂度;该文借鉴机器学习过程,构建了具备学习能力的智慧蚁群模型,提出了智慧蚁群优化算法,通过对训练样本的映射学习,持续优化初始化信息素浓度矩阵,提升算法映射收敛速度,以已知算法映射指导未知算法映射,实现密码算法映射的智能化.实验结果表明,本文提出的映射方法能够平均降低编译时间37.9%并实现密码算法映射性能最大,同时,以算法数据流图作为映射输入,自动化的生成密码算法映射流,提升了密码算法映射的直观性与便捷性.     

基于动态可重构的FFT处理器的设计与实现

提出了一种基于局部动态可重构(DPR)的新型可重构FFT处理器.相比传统的FFT设计,该设计方法在重构时间上得到了很大改进,同时,处理器能够动态地添加或移除重构单元.采用新颖的FFT控制算法,使得可重构部分面积很小.该处理器结构在Xilinx Viirtex2p系列FPGA上进行了综合及后仿真.较之Xilinx IPcore,其运算效率明显提高,而且还实现了IP核所不具备的动态可重构性.     

Multicore Flow Processor with Wire‐Speed Flow Admission Control

We propose a flow admission control (FAC) for setting up a wire‐speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial‐of‐service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65‐nm CMOS technology and has a 40‐Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss.     

高吞吐率双模浮点可重构FFT处理器设计实现

高吞吐浮点可灵活重构的快速傅里叶变换(FFT)处理器可满足尖端雷达实时成像和高精度科学计算等多种应用需求。与定点FFT相比,浮点运算复杂度更高,使得浮点型FFT的运算吞吐率与其实现面积、功耗之间的矛盾问题尤为突出。鉴于此,为降低运算复杂度,首先将大点数FFT分解成若干个小点数基2k 级联子级实现,提出分别针对128/256/512/1024/2048点FFT的优化混合基算法。同时,结合所提出同时支持单通道单精度和双通道半精度两种浮点模式的新型融合加减与点乘运算单元,首次提出一款高吞吐率双模浮点可变点FFT处理器结构,并在28 nm标准CMOS工艺下进行设计并实现。实验结果表明,单通道单精度和双通道半精度浮点两种模式下的运算吞吐率和输出平均信号量化噪声比分别为3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。归一化吞吐率面积比相比于现有其他浮点FFT实现可提高约12倍。     

High‐Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area‐Throughput Trade‐Offs

This paper presents two types of high‐speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area‐throughput trade‐offs are evaluated depending on the S‐box implementation by using look‐up tables or combinational logic which involves composite field arithmetic. The sub‐pipelined architectures for non‐feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S‐box implementation using composite field arithmetic over GF(2⁴)², throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub‐pipelined architecture of ARIA for high throughput to date.     

面向分组密码的可重构异构多核并行处理架构

现有的可重构分组密码实现结构中,专用指令处理器吞吐率不高,阵列结构资源利用率低、算法映射过程复杂.为此,设计了分组密码可重构异构多核并行处理架构RAMCA（Reconfigurable Asymmetrical Multi-Core Architecture）,分析了典型SP（AES-128）、Feistel（SMS4）、L-M（IDEA）及MISTY（KASUMI）结构算法在RAMCA上的映射过程.在65nm CMOS工艺下完成了逻辑综合和功能仿真.实验表明,RAMCA工作频率可达到1GHz,面积约为1.13mm²,消除工艺影响后,对各分组密码算法的运算速度均高于现有专用指令处理器以及Celator、RCPA和BCORE等阵列结构密码处理系统.     

A RISC architecture extended by an efficient tightly coupled reconfigurable unit

In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain reconfigurable functional unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits instruction level parallelism (ILP) and spatial computation. Also, the proposed integration of the RFU efficiently exploits the pipeline structure of the processor, leading to further performance improvements. Furthermore, a development framework for the introduced architecture is presented. The framework is fully automated, hiding all reconfigurable hardware related issues from the user. The hardware model of the architecture was synthesized in a 0.13?µm process and all information regarding area and delay were estimated and presented. A set of benchmarks is used to evaluate the architecture and the development framework. Experimental results prove performance improvements in addition to potential energy reduction.