Reliability of 50 nm low-noise metamorphic HEMTs and LNAs

The long-term stability of a 50 nm low-noise metamorphic HEMT technology has been investigated by biased accelerated lifetime tests on both MHEMT devices and two-stage LNAs for W-band applications. The lifetime tests were performed at three channel temperatures, a drain voltage of 1 V and a power density of 0.3 W/mm in air. Based on a -10% degradation of g/sub m max/ failure criterion an activation energy of 1.6 eV and a projected median lifetime of 2.7/spl times/10/sup 6/ h at T/sub ch/=125/spl deg/C were determined. The two-stage LNAs were stressed at a channel temperature of 185/spl deg/C for 4000 h. The S-parameters did not show any significant degradation after 4000 h of stress time if the positive threshold voltage shift was compensated for by a corresponding increase of the gate voltage. The reliability results demonstrate the stable operation of 50 nm MHEMTs and LNAs for W-band applications and beyond.     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Improved lifetime of poly-Si TFTs with a self-alignedgate-overlapped LDD structure

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H₂ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation     

Hot-carrier effects in P-channel modified Schottky-barrier FinFETs

High-performance p-channel modified Schottky-barrier SOI FinFETs (MSB pFinFETs) with low temperature source/drain annealing process was recently suggested for future nano-scale devices. In this letter, the hot-carrier (HC) immunity of the MSB pFinFETs with different gate lengths (L/sub g/) and fin widths (W/sub f/) are presented. The experimental data shows that the MSB pFinFET with narrower W/sub f/ has less hot carrier degradation than that with wider W/sub f/. The effects of electrical field in Si fins induced from lateral-gate electrode and the degree of uniformity of source/drain extension are illustrated cautiously by two-dimensional simulation and transmission electron microscopy (TEM) micrographs, respectively. It is found that the devices with narrower W/sub f/ have weaker electrical field from gate electrode and better uniformity of source/drain extension resulting in superior hot-carrier immunity. The projected operation voltage at ten years dc lifetime exceeds 1.6 V as the W/sub f/ is narrower than 60 nm. It is thus concluded that the MSB pFinFET would be a very promising nano device.     

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd

Hot-carrier degradation of n-MOSFETs at high gate voltages (V_g=V_d) is examined. A new lifetime prediction method is developed based on the universal power law between the degradation of saturated drain current (dI_dsat) and the product of the injected charge fluence times the gate current, which is independent of gate or drain voltages. This method is applied to 4 and 5 nm n-MOSFETs and lifetimes are estimated under their operation conditions. It is applicable to n-MOSFETs with ultrathin gate oxides.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

XeBr XeCl激光同时振荡的研究

本文报道了由ＨＣｌ／ＨＢｒ／Ｘｅ／Ｎｅ体系获得的ＸｅＢｒ与ＸｅＣｌ两种激光（２８２ｎｍ，３０８ｎｍ）同时振荡。对同时振荡的过程作了初步的分析，并在单独振荡的情况下研究了ＨＣｌ对ＸｅＢｒ激光能量及寿命的影响与ＨＢｒ对ＸｅＣｌ激光能量及寿命的影响。     

Hot-carrier-reliability design rules for translating devicedegradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at V_gs=V_ds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft_rise and 10/ft_fall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively     

基于传输距离和Sink移动的扩延网络寿命算法

在无线传感网络WSN(Wireless Sensor Network)中,传感节点通常以多跳方式向信宿Sink传输感测数据.由于邻近信宿Sink的传感节点需要承担数据转发的任务,比其他节点消耗更多的能量,缩短了网络寿命.为此,提出一种扩延网络寿命的新算法,记为NLTA(Network LifeTime Augmentation).NLTA算法采用了节点传输距离自适应调整和信宿Sink移动两个策略.节点依据能量情况,调整传输距离,减少能量消耗,然后根据路径容量值,调整Sink的位置,平衡网内的节点能量消耗,避免信宿Sink的周围节点能量过度消耗.仿真结果表明,提出的NLTA方案能够有效地提高网络寿命.     

Lifetime reliability of thin-film SOI nMOSFET's

The dc device lifetime reliability of thin-film SOI MOSFET's is investigated over a wide range of drain stress from just below the SOI breakdown voltage up to typical accelerated stress voltages. Unique hot-carrier degradation behaviors were observed for different ranges of applied drain stress. The degradation behavior and mechanism are found to dynamically change from one type observed under low drain stress (realistic operation range) to a different type observed under high drain stress (strong breakdown operation). This causes the SOI MOSFET to exhibit a two slope lifetime versus reciprocal drain voltage behavior which could have strong implications on the hot-carrier stressing methodology and reliability study of these devices     

Er:GSGG 晶体的光谱性质分析及激光特性模拟研究

测试和分析了Er:GSGG的吸收光谱和荧光光谱。应用Judd-Ofelt理论计算了Er3+的强度参数、自发辐射跃迁几率、能级寿命、荧光分支比和吸收截面。结果表明,Er3+在4I13/2和4I11/2能级有较长的能级寿命,在966nm和790nm处有较大的吸收截面,在2.79µm处有较大的积分发射截面值,数值模拟了在966nm泵浦下激光输出特性,在泵浦速率达到一定值时,有较高的量子效率。结果表明Er:GSGG有望成为2.79µm波段的理想激光晶体。     

Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling

For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.     

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFET's

A new two-dimensional device simulator is developed to investigate the effects of velocity overshoot on Si MOSFET's. An electron temperature-dependent mobility model, in which mobility is determined as a function of electron-gas temperature, is used in the simulator. Marked velocity overshoot occurs in the vicinity of the drain edge of MOSFET's and makes the potential barrier height at the source edge lower for ultrashort-channel MOSFET's. Therefore, velocity overshoot effects appear not only as degradation of electron transit time but also as increased drain current as compared with the case in which drift velocity does not overshoot. The increase in drain current depends strongly upon low-field mobility and bias conditions and appears for channel lengths shorter than 1000 nm. When low-field mobility is higher than 500 cm²/V. s and channel length is 100 nm, the increase in drain current is more than 1.5 times for bias conditions of strong inversion and a lateral electric field of more than 10⁵V/cm in the vicinity of the drain edge.     

High resolution transport spectroscopy in ultimate MOSFETs at very low temperature

To analyse electrostatic disorder in doped sub-100 nm Si-MOSFET channels we investigate the sub-threshold regime by transport spectroscopy at very low temperature. We measure resonances in the differential drain current and analyse their distribution in gate voltage, which is found to be gaussian. The mean value is interpreted as the electrostatic charging energy associated to a local well in the surface potential, whose dimensions is comparable to the channel length. The channel dopants concentration does not affect significantly this result.     

Impact of ultrashallow junction on hot carrier degradation ofsub-0.25-μm nMOSFETs

We have investigated the hot carrier (HC) reliability of nMOSFETs with an ultrashallow source/drain (S/D) extension, and found that lightly doped drain (LDD)-type HC degradation is accelerated. The lifetime strongly depends on the extension implantation dose or the implantation angle. A reduced overlap region between the gate electrode and drain diffusion seemed to exaggerate the LDD-type HC degradation. Angled implantation at over 10° effectively suppressed the degradation     

Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs

We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 10⁶ and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications     

Routing mechanisms for mobile ad hoc networks based on the energy drain rate

Untethered nodes in mobile ad hoc networks strongly depend on the efficient use of their batteries. In this paper, we propose a new metric, the drain rate, to forecast the lifetime of nodes according to current traffic conditions. This metric is combined with the value of the remaining battery capacity to determine which nodes can be part of an active route. We describe new route selection mechanisms for MANET routing protocols, which we call the minimum drain rate (MDR) and the conditional minimum drain rate (CMDR). MDR extends nodal battery life and the duration of paths, while CMDR also minimizes the total transmission energy consumed per packet. Using the ns-2 simulator and the dynamic source routing (DSR) protocol, we compare MDR and CMDR against prior proposals for energy-aware routing and show that using the drain rate for energy-aware route selection offers superior performance results. Methods keywords are system design and simulations.