共查询到20条相似文献,搜索用时 15 毫秒
1.
N. Badereddine Z. Wang P. Girard K. Chakrabarty A. Virazel S. Pravossoudovitch C. Landrault 《Journal of Electronic Testing》2008,24(4):353-364
Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power
consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang
Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International
Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction
for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits
with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The
proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number
of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained
simultaneously.
相似文献
C. LandraultEmail: URL: URL: http://www.lirmm.fr/~w3mic |
2.
Haiying Yuan Changshi Zhou Xun Sun Kai Zhang Tong Zheng Chang Liu Xiuyu Wang 《Journal of Electronic Testing》2018,34(6):685-695
Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits. 相似文献
3.
This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment.Meanwhile,our paper also introduces a novel algorithm of scan-block clustering.The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding.Thus,it can significantly reduce the test power and test data volume.Experimental results using Mintest test set on the larger ISCAS’89 benchmarks show that the proposed method reduces the switching activity significantly by 72%-94%and provides a best possible test compression of 74%-94%with little hardware overhead. 相似文献
4.
Ozgur Sinanoglu 《Journal of Electronic Testing》2008,24(5):439-448
While integrated circuits of ever increasing size and complexity necessitate larger test sets for ensuring high test quality,
the consequent test time and data volume reflect into elevated test costs. Test data compression solutions have been proposed
to address this problem by storing and delivering stimuli in a compressed format. The effectiveness of these techniques, however,
strongly relies on the distribution of the specified bits of test vectors. In this paper, we propose a scan cell partitioning
technique so as to ensure that specified bits are uniformly distributed across the scan slices, especially for the test vectors
with higher density of specified bits. The proposed scan cell partitioning process is driven by an integer linear programming
(ILP) formulation, wherein it is also possible to account for the layout and routing constraints. While the proposed technique
can be applied to increase the effectiveness of any combinational decompression architecture, in this paper, we present its
application in conjunction with a fan-out based decompression architecture. The experimental results also confirm the compression
enhancement of the proposed methodology.
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
Ozgur SinanogluEmail: |
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
5.
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing 总被引:1,自引:1,他引:0
Xiaoqing Wen Kohei Miyase Tatsuya Suzuki Seiji Kajihara Laung-Terng Wang Kewal K. Saluja Kozo Kinoshita 《Journal of Electronic Testing》2008,24(4):379-391
At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However,
at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity.
This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching
activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while
the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a
novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static
compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage
loss, and additional design effort.
相似文献
Xiaoqing WenEmail: |
6.
This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires
only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable
network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression
is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark
circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.
相似文献
Hideo ItoEmail: |
7.
Hua-Guo Liang Sybille Hellebrand Hans-Joachim Wunderlich 《Journal of Electronic Testing》2002,18(2):159-170
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility. 相似文献
8.
In this paper, we show that not every scan cell contributes equally to the power consumption during scan-based test. The transitions
at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells.
Hence the transitions at these scan cells have a larger impact on the power consumption during test application. We call these
scan cells power sensitive scan cells. A signal probability based approach is proposed to identify a set of power sensitive
scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order
to reduce the shift power consumption. Experimental results on industrial circuits show that on average more than 45% of the
scan shift power can be eliminated when freezing only 5% of power sensitive scan cells.
相似文献
Yu HuangEmail: |
9.
This paper discusses an automated method to divide scan chains into multiple scan segments that are suitable for power-constrained
at-speed testing using the skewed-load test application strategy. By dividing a circuit into multiple partitions, which can
be tested independently, both power during shift and power during capture can be controlled. Despite activating one partition
at a time, we show how through conscious construction of scan segments, high transition fault coverage can be achieved, while
reducing test time of the circuit and employing third party test generation tools.
相似文献
Nicola NicoliciEmail: |
10.
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Ozgur Sinanoglu 《Journal of Electronic Testing》2008,24(4):335-351
Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent
test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power
thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that
can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification
technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce
the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact
of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully
modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power.
The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification,
which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
Ozgur SinanogluEmail: |
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
11.
With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential
in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating,
which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead.
Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement
of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.
相似文献
Kaushik RoyEmail: |
12.
Ramyanshu Datta Ravi Gupta Antony Sebastine Jacob A. Abraham Manuel d’Abreu 《Journal of Electronic Testing》2008,24(5):481-496
Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs),
designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However,
DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs.
In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing.
Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation
significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces
the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits
with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation
during scan operation.
相似文献
Manuel d’AbreuEmail: |
13.
This work presents an M-ary multiple access code-selected direct sequence (DS) ultra wideband (UWB) communication system. A high data rate multiple
access UWB system can be obtained by a code selection mechanism. In the proposed system, each user is assigned a DS code set
with M/2 DS code sequence and a particular DS code sequence can be selected by the log2 (M/2) bits from the DS code set. More importantly for this M-ary UWB communication system, with the increase of the modulation level M, it allows to reduce the required transmitter power maintaining the number of users, the data transmission rate and the multiple
access performance. In this paper, we also introduce the detailed algorithm to compute the bit error rate (BER) over the AWGN
channel and correlation receivers.
相似文献
Kyungsup KwakEmail: |
14.
随着集成电路制造工艺的发展,VLSI(Very Large Scale Integrated)电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗. 相似文献
15.
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters 总被引:1,自引:1,他引:0
Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper,
a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing
approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the
proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment.
During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are
estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As
opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require
the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in
simulations as well as in hardware with specification estimation error of less than 5%.
相似文献
Shalabh GoyalEmail: |
16.
Grzegorz Mrugalski Janusz Rajski Chen Wang Artur Pogiel Jerzy Tyszer 《Journal of Electronic Testing》2007,23(1):35-45
This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction.
The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination
method.
相似文献
Jerzy Tyszer (Corresponding author)Email: |
17.
This paper presents a family of uniform random number generators designed for efficient implementation in Lookup table (LUT)
based FPGA architectures. A generator with a period of 2
k
− 1 can be implemented using k flip-flops and k LUTs, and provides k random output bits each cycle. Each generator is based on a binary linear recurrence, with a state-transition matrix designed
to make best use of all available LUT inputs in a given FPGA architecture, and to ensure that the critical path between all
registers is a single LUT. This class of generator provides a higher sample rate per area than LFSR and Combined Tausworthe
generators, and operates at similar or higher clock-rates. The statistical quality of the generators increases with k, and can be used to pass all common empirical tests such as Diehard, Crush and the NIST cryptographic test suite. Theoretical
properties such as global equidistribution can also be calculated, and best and average case statistics shown. Due to the
large number of random bits generated per cycle these generators can be used as a basis for generators with even higher statistical
quality, and an example involving combination through addition is demonstrated.
相似文献
Wayne LukEmail: |
18.
B. Balamuralithara 《Wireless Personal Communications》2009,49(1):15-22
In this paper, a modified unequal power allocation scheme for the different bits of asymmetric turbo encoder has been investigated
to enhance the performance. The simulation results and performance bound for the asymmetric turbo code with modified Unequal
Power Allocation (UPA) scheme are obtained and compared with the system with typical UPA and without UPA. From the performance
results, it is observed that the proposed asymmetric turbo code with modified UPA performs better than the system without
UPA and with typical UPA and it provides a coding gain of 0.4–0.52 dB.
相似文献
B. BalamuralitharaEmail: |
19.
Khoa N. Le 《Wireless Personal Communications》2008,47(3):355-362
This letter derives the upper and lower bounds on inter-carrier interference power P
ICI of Orthogonal Frequency Division Multiplexing (OFDM) in a Gaussian scattering channel. The bounds are computed as functions
of f
d
T
s
product of the maximum Doppler spread f
d
and symbol duration T
s
, ζ frequency tracking and ϵ mobile travelling direction. Insightful discussions on the characteristics of P
ICI are given. Future work is also outlined.
相似文献
Khoa N. LeEmail: |
20.
A peak-to-average power ratio (PAPR) reduction scheme with low complexity is proposed for the multicarrier spread spectrum
(MC-SS) system in personal area network (PAN). Traditional clipping and filtering scheme requires a high oversampling rate
to meet the emission mask requirements. This would cause high power consumption for mobile PAN devices in personal network.
To solve the problem, upsampling is introduced between clipping and filtering in this paper to reduce the oversampling rate.
A simplified implementation structure is also derived for the proposed scheme. Simulation results show that its complexity
is about 65% of the conventional scheme while achieving satisfying performance.
相似文献
Lu RongEmail: |