并口JTAG仿真器的设计与实现

通过对JTAG协议和标准并口规范的研究,提出了适合嵌入式系统调试的并口JTAG仿真器的实现方案.给出了硬件电路的设计,并通过并口信号的软件时序模拟实现底层通信从而完成JTAG协议的转换,最后提出开放接口的驱动软件架构,可以对目标机器进行在线编程和调试,实现人机交互以及与第三方开发工具的交互,并对基本功能进行了验证.     

EPM7128LSC84在控制并口电路设计中的应用

本文介绍了MAX+PLUSII工作平台下使用VHDL硬件描述语言设计控制系统接口的方法,对并口电路的资源进行了规划,给出了用可编程EPM7128LSC84实现控制并口电路的设计、编程与结果仿真。     

基于FPGA和EPP的芯片测试电路设计

提出了一种基于FPGA和EPP并口的模数转换器芯片测试电路设计。通过FPGA实现了对待测试芯片的数据读出和控制,并将数据进行相关处理,再通过EPP并口模块与计算机系统连接,实现了待测试芯片与计算机的双向通信,其通信速率达到1.2MB/s。在介绍芯片测试电路各个模块电路的基础上,详细讲述了测试芯片所集成的2种模数转换器电路、信号处理电路以及EPP并口的功能及实现原理。本设计已经应用于实际的芯片测试系统中,其性能良好,工作稳定,达到了预期的设计目标。     

基于80C51型单片机和CH375型接口电路的LPT-USB打印机驱动器的设计与实现

介绍基于80C51型单片机与CH375型接口电路的LPT-USB打印机驱动器的设计与实现方法,介绍CH375型USB总线通用接口电路的特点及工作原理,给出80C51通过CH375控制USB打印机的硬件设计及其C语言软件.利用该设计能够实现并行打印口数据在USB打印机直接打印,克服了有些并口仪器必须连接并口打印机才能打印的弊端,给用户提供了方便.     

Gkv Intel 386TM EX的JTAG口对Flash编程

介绍了通过jTAG口实现对Flash在系统编程。首先，对Intel 386^TMEX的逻辑测试单元进行了阐述；然后，分析了通过JTAG口编程Flash的原理及性能；最后，给出了通过JTAG口对Flash在系统编程的并口转换接口电路，并给出了编程思路和程序流程图。     

一种SRAM单双端口转换电路的设计与实现

介绍了一种用于单端口SRAM的单双端口转换电路.利用该转换电路,可以使单端口SRAM实现双端口SRAM的功能.这种转换电路将外部两个端口的信号进行转换和优先权分配,使外部两个端口的并行操作在内部用单端口SRAM依次完成.这样,从外部看来,单端口SRAM就具有了双端口SRAM的全部功能.用这种转换电路生成的双端口SRAM与相同容量的传统双端口SRAM相比,面积显著减少.基于SMIC 0.13μm标准CMOS工艺,设计了转换电路.后仿真结果显示,该转换电路实现了预期功能.     

连接计算机并口的数据采集系统

针对目前大多数导弹测试数据都从测试计算机并口输出,设计了基于单片机对测试数据进行并口采集的系统,通过介绍打印机的工作模式和工作时序,给出了并口数据采集的原理、系统的接口电路和软件编程的流程图,且给出了中断程序的代码,最后通过用样本数据调试系统,证实该系统数据接收效果令人满意、实时性好。     

用于电力监控系统的同步采样ADC

AD7606和AD7607同步采样ADC包含LDO、基准电压和缓冲器、跟踪与保持电路、信号调理电路、片上转换时钟以及高速并口和串口。这些新型器件还内置低噪声、高输入阻抗（独立于采样率）信号调整放大器，其-3dB输入带宽为10kHz，模拟输入阻抗为1MΩ，增益误差仅为0．1％，失调误差仅为0．01％。     

扩展EPP接口

PC机并行接口的EPP方式（IEEE1394）的推出给用户带来了极大的方便。但是EPP提供的口地址很少，特别是外部电路中有多个口地址需要与EPP接口时，极为不便。笔者在使用EPP方式采集一个多AD系统的实验中，设计了一个使用EPP方式下一个口地址来读写多片AD的扩展接口电路，该电路十分简单，但非常实用。PC并口的37BH口扩展电路图1是PC机并口EPP方式下的37I3H口地址的扩展接口电路，其工作原理是利用了EPP的一个口地址形成了若干个连续口地址。如图所示扩展电路由161和138组成。161的CLK输入端接EPP的17脚，ABCD端可随意调整…     

一种用于UHF RFID的低压高效电源产生电路

介绍了一种为无源UHF RFID设计的高效高灵敏度电源产生电路.该电路基于0.18μm工艺,其中包含了两个电荷泵,一个参考电流源和一组偏置电路.由于其偏置电路消除了传统电路中的阈值损失和体效应,使该电路在低压下的电源转换性能得到很大的提高.要为100kΩ负载提供1.5V电源电压,所需最小输入电压为350mV,转换效率为22%.在负载为60kΩ时,最高可以获得29.8%的转换效率.仿真结果表明,新的电路结构比传统的电荷泵具有更优越的性能.     

NODIFS-simulating faults fast

This article introduces, perhaps for the first time, an asynchronous, distributed, circuit partitioned algorithm that is capable of fault simulating both combinational and sequential digital designs on parallel processors. In this approach, called NODIFS (NOvel asynchronous DIstributed algorithm for Fault Simulation), every circuit component is modeled as an asynchronous and concurrent entity that is checked for faults as soon as appropriate signal transitions and fault lists are asserted at its input ports. The circuit is partitioned such that components of every partition are allocated to a unique processor of the parallel processor system     

低损耗梳状声表面波延迟线的耦合模分析

梳状换能器可看成若干叉指单元电端并联,声端首尾串联而成的网络,采用单向结构可降低采用这种结构的声表面波延迟线的损耗。根据耦合模(COM)理论推导出整个换能器的混合矩阵(P矩阵)并结合等效电路模型得到了整个延迟线二端网络的导纳矩阵以及延迟线的幅频及相频响应。本方法能模拟指间反射、三次行程、指条寄生阻抗以及外围电路对器件的影响;理论模拟与实验结构吻合。     

UHF Strip Transmission Line Hybrid Junction

A hybrid junction has been developed using a symmetrical strip transmission line for application in the UHF range. It has a frequency band of +- 20 per cent where the input voltage standing-wave ratios at all ports are less than 1.26 (2 db), the power divisions are within 0.1 db, and the difference in power between the series input and parallel input ports is less than 0.3 db. The isolation is greater than 40 db and 24 db, respectively, for the two pairs of conjugate ports. These circuits are relatively small, light-weight, simple to build and reproduce, and are inexpensive. The approximate equivalent circuit of the configuration assuming transmission in the TEM mode is presented. The results of the analysis and the important features in the design and fabrication and a few modifications of the configuration are discussed.     

Passive broadband millimetre-wave uniplanar MMIC balun

A new uniplanar monolithic microwave integrated circuit (MMIC) balun using lumped circuits is presented. The proposed planar balun consists of a wideband Wilkinson power divider and a broadband 180° phase shifter using novel series and parallel LC reflective terminating circuits. To demonstrate the design methodology, a 24?44 GHz MMIC balun was realised as a 1.4 mm _{GaAs chip. The measured return losses for the unbalanced and balanced ports are better than 212, 210 and 27 dB, respectively. The measured amplitude and phase imbalance between the two output ports are less than 0.5 dB and 7°, respectively, and maximum insertion loss is 5 dB.}     

N-Way TEM-Mode Broad-Band Power Dividers

An integrative graphical method of designing a broadband TEM-mode power divider of N output ports is presented. Each branch of the divider's circuit consists of cascaded transmission-line segments, and the corresponding segments of each branch are connected by resistors to a common junction. These resistors absorb the reflected signals due to mismatch at any of the output ports; they are therefore isolated from one another. The symmetry of this circuit permits the use of the method of even- and odd-mode excitations at the output ports. It was found that the even-mode circuit is the same as for a stepped-impedance transformer, which is well known. The odd-mode circuit lends itself to the determination of the isolation resistors using the iterative graphical procedure on a Smith chart. Numerical values of the isolation conductance for dividers of bandwidths up to 10:1, the maximum input VSWR, and the minimum isolation among the output ports are given.     

Hybrid S-Parameters for Transmission Line Networks With Linear/Nonlinear Load Terminations Subject to Arbitrary Excitations

We propose a generalized S-parameter analysis for transmission lines (TLs) with linear/nonlinear load terminations subject to arbitrary plane-wave and port excitations. S-parameters are prevalently used to model TLs such as cable bundles and interconnects on printed circuit boards (PCBs) subject to port excitations. The conventional S-parameter approach is well suited to characterize interactions among ports. However, nontraditional port excitations associated with plane-wave coupling to physical ports at TL terminals lead to forced, as well as propagating, modal waves, necessitating a modification of the standard S-parameter characterization. In this paper, we consider external plane-wave excitations, as well as port (internal) sources, and propose a hybrid S-parameter matrix for characterization of the associated microwave network and systems. A key aspect of the approach is to treat the forced waves at the ports as constant voltage sources and induced propagating modal waves as additional entries (hybrid S-parameters) in the S-parameter matrix. The resulting hybrid S-matrix and voltage sources can be subsequently exported to any circuit solver such as HSPICE and Agilent's Advanced Design System for the analysis of combined linear and nonlinear circuit terminations at ports. The proposed method is particularly suited for susceptibility analysis of cable bundles and PCBs for electromagnetic interference evaluations. It also exploits numerical techniques for structural and circuit domain characterization and allows for circuit design optimization without a need to perform any further computational electromagnetic analysis     

一种多音圈式全数字扬声器的设计与实现

提出了一种由USB数字音频接口、数字开关电流源电路和多音圈式换能器构成的数字扬声器设计方案。USB数字音频接口将WAV文件转换为并行数字信号输出,数字开关电流源电路根据数字信号控制相应位音圈的通断,多音圈式换能器按匝数权值实现电流到声音的转换。实验结果表明,在声音效果相同的情况下,和传统扬声器相比,数字扬声器具有低功耗,强抗干扰能力等优点,充分说明了该方案的可行性及良好的应用前景。     

二端口元件的电阻替代方法及其应用

针对含二端口元件的电路,提出了用电阻支路替代二端口元件端口的分析方法。经过电阻替代后,消除了二端口元件端口间的耦合关系,从而使得电路的分析显得直观、简单。讨论了电阻替代方法的适用性条件。通过举例说明了该方法在电路分析中的应用。     

基于多串口扩展技术的定点剖面观测系统设计

为了满足定点剖面测量系统多个串口通信的需要,设计了一种基于ATmegal28L的多串口扩展电路。详细介绍了该电路的硬件设计和部分软件代码。该电路将TI公司的异步串口芯片TLl6C754用于ATmegal128L的串口扩展,可以扩展4路串口。扩展的串口分别与海流计、CTD、浮力调节系统、水声通信系统连接,进行串口通信,传送控制指令和测试数据。实际应用证明,该电路设计可靠,稳定性好,解决了ATmegal128L在串行通信系统中的串口数量的局限性。     

A super parallel sorter using a binary neural network with AND-OR synaptic connections

This paper presents an ultra-high-speed sorter based upon a simplified parallel sorting algorithm using a binary neural network which consists both of binary neurons and of AND-OR synaptic connections to solve sorting problems at two and only two clock cycles. Our simplified algorithm is based on the super parallel sorting algorithm proposed by Takefuji and Lee. Nevertheless, our algorithm does not need any adders, while Takefuji's algorithm needs n×(n–1) analog adders of which each has multiple input ports. For an example of the simplified parallel sorter, a hardware design and its implementation will be introduced in this paper, which performs a sorting operation at two clock cycles. Both results of a logic circuit simulation and of an algorithm simulation show the justice of our hardware implementation even if in the practical size of the problem.