Compact Microracetrack Resonator Devices Based on Small SU-8 Polymer Strip Waveguides

Compact microracetrack resonator (MRR) devices are presented with small SU-8 polymer strip waveguides. The SU-8 strip waveguide has an SU-8 polymer core $(n {sim} 1.573)$ , a SiO$_{2}$ buffer $(n {sim} 1.445)$, and an air cladding. The fabricated straight waveguide has a low propagation loss of about 0.1 dB/mm. With such a high index-contrast optical waveguide, a compact MRR with a small bending radius ( $sim$150 $mu$m) are designed and fabricated. The measured spectral responses of the through/drop ports show a $Q$-factor of 8000.      

10-GHz and 20-GHz Channel Spacing High-Resolution AWGs on InP

This letter reports on 10-GHz and 20-GHz channel-spacing arrayed waveguide gratings (AWGs) based on InP technology. The dimensions of the AWGs are 6.8$,times,$8.2 mm$^{2}$ and 5.0$,times,$6.0 mm$^{2}$, respectively, and the devices show crosstalk levels of $-$12 dB for the 10-GHz and $-$17 dB for the 20-GHz AWG without any compensation for the phase errors in the arrayed waveguides. The root-mean-square phase errors for the center arrayed waveguides were characterized by using an optical vector network analyzer, and are 18 $^{circ}$ for the 10-GHz AWG and 28$^{circ}$ for the 10-GHz AWG.      

InGaAs/GaAs 0.98- $mu{hbox {m}}$ Low-Divergence Central-Lobe Semiconductor Lasers With $delta$ -Doped Resonant Tunneling Quantum Wells

In this paper, we describe a new structure design for producing low-threshold, high-efficiency, and high-brightness 0.98-$mu{hbox {m}}$ lasers. In this structure, we incorporated a self-discriminating weak optical confinement asymmetrical waveguide coupled to passive waveguides, and an active region based on three InGaAs quantum wells (QWs) coupled to Te n-type $delta$-doping. Optimized coupling between the $delta$-doping and the three QWs, together with waveguide optimization and doping profile optimization, yields $J_{rm th}=98 {hbox {A/cm}}^{2}$ per QW, ${T}_{0}=80;^{circ}hbox{C}$, and a far-field central lobe angle of $sim 10^{circ}$.      

Enhanced Transmission in a Fiber-Coupled Au Stripe Waveguide System

We experimentally demonstrated the enhanced transmission in a fiber-coupled Au stripe waveguide system using a linearly tapered (LT) structure at a telecommunication wavelength of 1.55 $mu{hbox {m}}$. The LT structure consists of two 100- $mu{hbox {m}}$-long tapered regions connecting various widths of input and output waveguides with a waist region. The lowest insertion loss of the 1-cm-long LT-Au stripe waveguide is $sim$4.3 dB, when it has 6-$mu{hbox {m}}$ -wide input and output waveguides and a 4- $mu{hbox {m}}$-wide waist waveguide. The insertion loss is reduced by $sim$ 2 dB compared to the 4-$mu{hbox {m}}$-wide and 1-cm-long straight Au stripe waveguide, which is achieved by decreasing the coupling loss. The losses of the LT region, which has a tapered angle of less than 0.3$^{circ}$ between the input–output waveguides and the waist waveguide, are smaller than 0.4 dB. We showed that the insertion loss of the Au stripe waveguide can be reduced by introducing the LT structure, which can also provide efficient mode conversion.      

A 0.1–5 GHz Cryogenic SiGe MMIC LNA

In this letter, the design and measurement of the first SiGe integrated-circuit LNA specifically designed for operation at cryogenic temperatures is presented. At room temperature, the circuit provides greater than 25.8 dB of gain with an average noise temperature $(T_{e})$ of 76 K $(NF=1 {rm dB})$ and $S_{11}$ of $-$ 9 dB for frequencies in the 0.1–5 GHz band. At 15 K, the amplifier has greater than 29.6 dB of gain with an average $T_{e}$ of 4.3 K and $S_{11}$ of $-$14.6 dB for frequencies in the 0.1–5 GHz range. To the authors' knowledge, this is the lowest noise ever reported for a silicon integrated circuit operating in the low microwave range and the first matched wideband cryogenic integrated circuit LNA that covers frequencies as low as 0.1 GHz.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

Bend-Free Optical Power Transfer Using Photonic Crystal Waveguide Arrays

We report the study of 2-D photonic-crystal waveguide arrays (PCWA) composed of $N$ identical waveguides coupled evanescently with each other. The coupling properties of the waveguide modes are investigated using coupled-mode theory and finite-difference time domain method. One straightforward application of such an analysis is to route input power from a central waveguide to side waveguides. As a result, appropriate designs of PCWAs may permit the realization of efficient, compact and novel devices. For instance, we show that power dividers, switchers, and Mach–Zehnder interferometers can be feasible using $N =3$ channels. On the other hand, $N =5$ waveguides can divide the input power by 1/4 at a distance of approximately 37.2 $ mu{hbox {m}} $. Waveguide bends and Y-type junctions are used heavily for power transfer but they are prone to scattering losses; hence, lowering the transmission efficiency. They can be eliminated by means of PCWAs in the design of optical power distribution through photonic circuits.      

A Two-Port Single-Mode Fiber–Silicon Wire Waveguide Coupler Module Using Spot-Size Converters

In this paper, the performance of a two-port single-mode fiber–silicon wire waveguide coupler module which utilizes an identical spot-size converter (SSC) at the input and output ports is reported. Each of the silicon (Si)-based SSCs comprised cascaded horizontal linear and vertical nonlinear up-tapers measured 300 and 200 $mu$ m in length, respectively, in a common silicon-on-insulator (SOI) substrate. The structural parameters of the tapers were designed for compactness and relaxed tolerance to fabrication errors. The total length of the two-port coupler module was 1000 $mu$ m plus the variable length of the wire waveguide connecting the two SSCs. The mode-field diameter (MFD) of the Si-wire waveguide, 0.32$,times,$0.46 $mu$m $^{2}$, was transformed to the diameter of 2.8$,times,$ 8.0 $mu$ m$^{2}$ at the wavelength of 1.55 $mu$ m (corresponding to an area expansion of about 150 times) and vice versa by the SSCs with a net transmission loss of 4.1 dB/port. The field-mismatch loss between the SSC and the single-mode fiber with the MFD of 5.2 $mu$m was 2.1 dB/port.      

High-Speed 2$, times ,$2 Switch for Multiwavelength Silicon-Photonic Networks–On-Chip

We report the fabrication and experimental verification of a multiwavelength high-speed 2$, times ,$ 2 silicon photonic switch for ultrahigh-bandwidth message routing in optical on-chip networks. The structure employs only two microring resonators in order to implement the bar and cross states of the switch. These states are toggled using an optical pump at 1.5-$mu$m wavelengths inplane with the waveguide devices, though electronic, rather than optical, control schemes are envisioned for more complex systems built from these devices. Experiments characterize bit-error-rate performance in the bar and cross states during static and dynamic operation. The all-optical demonstration exhibits the ability of the switch to implement ultra-short transition times ( $≪ $2 ns), high extinction ratios ($>$10 dB), and low power penalties (${sim} 1$ dB) at a data rate of 10 Gb/s. Further performance improvements are expected by using electronic carrier injection via p-i-n diodes surrounding the ring waveguides. The 2$, times ,$2 switching functionality facilitates the design of more complex routing structures, allowing the implementation of high-functionality integrated optical networks.      

Near-Stoichiometric Ti : LiNbO$_{3}$ Strip Waveguides Fabricated by Standard Ti Diffusion and Post-VTE

We report near-stoichiometric (NS) Ti : LiNbO$_{3}$ waveguides fabricated by indiffusion of 4-, 5-, 6-, 7- $mu{hbox {m}}$-wide 120-nm-thick Ti-strips at 1060 $^{circ}hbox{C}$ for 10 h into a congruent $hbox{LiNbO}_{3}$ (i.e., standard Ti diffusion procedure) and post-vapour-transport-equilibration (VTE) treatment at 1100 $^{circ}hbox{C}$ for 5 h. These waveguides are NS and single-mode at 1.5 $mu{hbox {m}}$, and have a loss of 1.0/0.8 dB/cm for the TM/TE mode. In the width/depth direction of the waveguide, the mode field follows a Gauss/Hermite–Gauss profile, and the Ti profile follows a sum of two error functions/a Gauss function. The post-VTE resulted in increase of diffusion width/depth by 2.0/1.0 $mu{hbox {m}}$. A two-dimensional refractive index profile in the guiding layer is suggested.      

A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 $mu$m process in an area of only 915$, times ,$915 $mu$ m$^{2}$ . Measurements show that Phoenix consumes 35.4 $~$pW in standby mode and 226 nW in active mode.      

Experimental Demonstration of Deeply-Etched SiO$_{2}$ Ridge Optical Waveguides and Devices

Deeply-etched ${hbox{SiO}}_{2}$ optical ridge waveguides are fabricated and characterized. A detailed discussion of the fabrication process (especially for the deep etching process) is presented. The measured propagation losses for the fabricated waveguides with different core widths range from $0.33sim {hbox {0.81}}~{hbox {dB}}/{hbox {mm}}$. The loss is mainly caused by the scattering due to the sidewall roughness. The losses in bending sections are also characterized, which show the possibility of realizing a small bending radius (several tens of microns). 1 $,times {rm N}$ ( ${rm N}=2$, 4, 8) multimode interference couplers based on the deeply-etched ${hbox{SiO}}_{2}$ ridge waveguide are also fabricated and show fairly good performances.      

Photonic Crystal Slab Waveguides Based on Antiresonant Reflecting Optical Waveguide Structures

A novel two-dimensional photonic crystal slab waveguide based on an antiresonant reflecting optical waveguide (ARROW) structure is proposed and designed. Lightwaves propagating in this waveguide are confined by antiresonance reflection vertically and the photonic band gap laterally. In order to obtain the characteristics of the ARROW-based photonic crystal waveguides, the three-dimensional finite-difference time-domain simulations are performed. With a lateral adiabatic taper, a coupling efficiency of 80.3% from a single-mode fiber to the ARROW-based photonic crystal waveguide of a single-line defect is obtained. In addition, propagation losses less than 10 dB/mm and bend losses of 0.23 and 0.39 dB/bend for the designed 60$^{circ}$ and 120$^{circ}$ bends are achieved at an operating wavelength of $1.55~mu{hbox {m}}$.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

Compact Variable ${rm TE}$-${rm TM}$ Polarization Splitter Based on Simplified Coherent Coupling in Lithium Niobate

A compact-sized electrically tunable ${rm TE}$- ${rm TM}$ mode splitter composed of a mode converter and an asymmetric Y-branch structure is presented. The asymmetric Y-branch consists of a straight and a bent waveguides to split two polarization modes based on the mode-sorting effect. To shorten the device length, a simplified coherently coupled-bending structure is utilized for the bent waveguide. Experimental results show that the device length is reduced about 52%, extinction ratios of both ${rm TE}$ and ${rm TM}$ modes are higher than 25 dB, yet the applied voltage is not significantly increased.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Equivalent Circuit Model for the Gate Leakage Current in Broken Down $hbox{HfO}_{2}/hbox{TaN/TiN}$ Gate Stacks

We propose an equivalent circuit model for the post-breakdown (BD) current–voltage ( $I$–$V$) characteristics in $hbox{HfO}_{2}/hbox{TaN/TiN}$ gate stacks in n-MOSFETs. The model consists of two opposite-biased diodes with series resistances and a shunt leakage path. The circuit admits analytical solution using the Lambert $W$-function and is tested for both negative and positive gate biases in the voltage range of $-$1.5 to $+$1.5 V. We also show the versatility of the proposed approach to deal with the post-BD $I$– $V$ when source and drain contacts are grounded or floating and analyze the obtained results in terms of the charge available for conduction.