Low-power tri-state buffer in MOS current mode logic

In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others.     

Computer modelling of bipolar logic gates

A basic approach to the computer modelling of large arrays of bipolar gates using continuous analytic expressions is presented. A program has been written which applies this principle. It can handle complex situations and is justified on grounds of efficiency with l.s.i. circuits.     

Differential current switch logic: a low power DCVS logic family

Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.     

Merged-transistor logic (MTL)-a low-cost bipolar logic concept

The authors describe a novel bipolar logic featuring a direct injection of minority carriers into the switching transistor. MTL is based on inverters having decoupled multicollector outputs for the logical combinations. The devices are self-isolated and no ohmic load resistors are required. This is a key to monolithic logic chips of very high functional density and low power dissipation. On experimental chips an excellent power-delay product of 0.35 pJ has been measured. These experiments show that a density of 100 gates/mm/SUP 2/ can be achieved with present manufacturing tolerances (minimum dimensions: 0.3-mil metal line width, 0.15-mil spacing, 0.2/spl times/0.2-mil/SUP 2/ contact holes).     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

Pseudo-complementary FET logic (PCFL): a low-power logic family inGaAs

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET's only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 μm MESFET process. The power consumption of an inverter is about 10 μW at 100 MHz     

Behavior of a radiation-immune CMOS logic family under resistiveshorts

Previous researchers had developed a special family of CMOS logic circuits which uses additional feedback transistors to provide immunity to radiation-induced errors for space-borne electronics. It was originally speculated that these transistors, representing a form of redundancy, might provide additional benefits, such as greater tolerance of manufacturing defects. Instead, the authors work shows that the redundant transistors, because of the way in which they are used, increase the sensitivity of the circuitry to manufacturing defects which manifest themselves as resistive transistor shorts, such faults cause: (1) logic errors at the affected gate output; and (2) an increase in the signal transition delay. Furthermore, these transistors lead to higher levels of quiescent supply current, making the circuits more difficult to test using quiescent current (I_DDQ) testing     

Current hogging logic (CHL)-a new bipolar logic for LSI

Logic functions of current hogging logic (CHL) are established by switching the lateral injection current in intermediate collector p-n-p structures. High functional density is achieved, since NOR, NAND, and complex gates can readily be realized and all logic elements can be placed within a common isolation region. CHL is fabricated with a standard buried collector process, and hence is compatible with linear bipolar circuits and other bipolar logic families. Current levels are employed as the logical variables, and the transfer characteristics of an AND-NOR gate are discussed. CHL offers high static and dynamic noise immunity. The paper demonstrates a static frequency divider as an example of an CHL circuit.     

Design and performance evaluation of management service logic execution environment in NGN

This paper introduces a mechanism to solve the service management quick provision problem in next generation network (NGN). The service management logic execution environment (MSLEE) is presented first. The MSLEE is independent of service management contents and network details. The structure of MSLEE with layered universal service management components is also proposed. Then the service management process with double logics is described to illuminate how MSLEE works. At last, MSLEE is modeled using Stochastic Petri net (SPN), and the performance of MSLEE is analyzed based on the simulation experiment with the help of SPNP simulation tool. The experiment result proved that MSLEE is feasible.     

MAIL-a new Josephson logic family

A novel family of Josephson logic circuits called magnetically coupled asymmetric interferometer logic (MAIL) has been designed. The basic MAIL device is an asymmetric two-Josephson-junction interferometer. Computer simulations of OR/AND MAIL circuits using 2.5 /spl mu/m Pb/Pb technology device models indicate an unloaded logic-gate delay of approximately 25 ps and a power dissipation of 5 /spl mu/W/gate. Thus, the power-delay product is only 125 Atto J. Different MAIL logic gates have been tested experimentally, and preliminary results are presented.     

Improved adiabatic pseudo-domino logic family

An improved input-isolation structure for APDL (adiabatic pseudo-domino logic) is proposed. The proposed circuit, IAPDL (improved APDL), provides a higher frequency performance in excess of 1 GHz with simple clock supplies. It is more compact compared with T-APDL (transmission gate-interfaced APDL) and the power dissipation is generally about half that of APDL. HSPICE simulations were performed and the results indicate that a reduction of up to 75% in power dissipation can be achieved compared to conventional CMOS     

A new RTD-FET logic family

We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules     

Physical timing models and design methodology of bipolar nonthreshold logic circuits

Physical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C_E and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C_E is equal to 1–1.25 C_E0 where C_E0 is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C_E0 have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.     

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.     

A voltage tunable threshold logic gate based on multiquantum-wellheterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing     

Reliability evaluation of logic circuits

An important guide in the project of logic circuits is the ability to estimate rightly its reliability. In this paper a new type of analysis is presented, by following the references [1], [2], [3] and the method implemented by [4]. This is applicable to all logic circuits, combinational or sequential and by this new structure a reliability matrix is obtained.     

Analysis of improved adiabatic pseudo-domino logic family

The authors show that when an improved adiabatic pseudo-domino logic circuit is used to perform complex logic, the circuit is susceptible to switching noise and logic failure