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1.
《Electron Devices, IEEE Transactions on》1987,34(3):581-586
Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p+-n or n+-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n+-p junctions (0.1-µm junction depth) and the Mo-silicided p+-n junction (0.16-µm junction depth) are comparable to that for unsilicided n+-p junction with greater junction depth ( ∼0.25 µm). 相似文献
2.
《Electron Device Letters, IEEE》1985,6(7):338-340
The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p+-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-V characteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2 -SiO2 interface are the contributing generation-recombination sites. 相似文献
3.
《Electron Devices, IEEE Transactions on》1987,34(3):575-580
The contact resistance between TiSi2 and n+-p+source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10-7and 1 × 10-6Ω . cm2can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 1020/cm3. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2 -n+and TiSi2 -P+interfaces. 相似文献
4.
《Electron Devices, IEEE Transactions on》1987,34(3):682-688
This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n+and p+junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n+and p+junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils2feasible with 1-µm design rules, is also discussed. 相似文献
5.
《Electron Device Letters, IEEE》1987,8(12):569-571
Shallow p+-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm2, indicating the possibility of this method to form PMOS source-drain contacts. 相似文献
6.
《Electron Devices, IEEE Transactions on》1986,33(10):1463-1469
We have examined the impact of TiSi2 formation on the properties of shallow n+and p+junctions (0.17-0.20 µm) in Si. The deposited Ti thickness varied from 300 to 1000 Å. The p+junctions developed high leakage currents after a reaction with Ti of initial thickness greater than 700 Å while the n+junctions were not degraded. In these studies LOCOS isolation was used and the TiSi2 was formed away from the island edges. Additional experiments were performed on n+and p+diodes using SWAMI isolation with the TiSi2 formed right up to the edges of the isolation. From step-height, spreading resistance, and RBS measurements, it was found that the thickness of TiSi2 formed on n+Si was less than on p+Si for a given initial Ti thickness. The amount of electrically active dopant remaining in the substrates was seen to decrease with increasing Ti thickness. The result was supported by SIMS measurements, which also showed an accumulation of atomic fluorine at the TiSi2 interface (on p+diodes only). Cross-sectional transmission electron microscopy was used to examine the silicide morphology and interface planarity. 相似文献
7.
《Electron Devices, IEEE Transactions on》1982,29(4):547-553
A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2 polycide gate. A coevaporated TiSi2 polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2 because of lower oxygen contamination. The coevaporation technique to form TiSi2 polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2 polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude. 相似文献
8.
《Electron Devices, IEEE Transactions on》1978,25(6):619-627
The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5 Ga0.5 As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 1017-cm-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 1018-cm-3Ge-doped Al0.5 Ga0.5 As gate layer and a p+-type 5 × 1018-cm-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p+-type GaAs and Al0.5 Ga0.5 As. Undercutting of the Al0.5 Ga0.5 As layer results in submicrometer gate lengths, and the resulting p+-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps. 相似文献
9.
《Electron Devices, IEEE Transactions on》1985,32(2):184-193
According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N+and P+diffusion and N+-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2 layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2 layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2 layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA. 相似文献
10.
Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p+/n diodes with junction depths below 100 nm. SiF4 is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF3 is implanted. Ultrashallow p+/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm 2 in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs 相似文献
11.
Ultra-shallow p+/n and n+/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi2 was implanted with As or with BF2 and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 -10 A/cm2 for p+/n and 2.7×10-9 A/cm2 for n+/p, respectively. The temperature dependence of the reverse current in the p +/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n+/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p+ /n junctions have an ideal behavior, while the n+/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi2, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n+/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness 相似文献
12.
A new technology of self-aligned TiN/TiSi2 formation using N2+ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n+/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi2 contact is 1.2 nA/cm2 at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi2 and Al for submicron CMOS technology applications 相似文献
13.
《Electron Devices, IEEE Transactions on》1987,34(8):1688-1693
Small-geometry CMOS devices with shallow n+and p+source-drain regions formed by arsenic and boron difluoride ion implantation, respectively, have been studied. Activation of implants was produced by a single rapid isothermal anneal using the multiple-scan electron-beam approach. Transistor and circuit simulations were used to determine a requirement for the source-drain region of a sheet resistance of < 100 Ω/square with a junction depth of less than 0.2 µm in 1-µm channel length devices. These values cannot be obtained by conventional furnace annealing at 950°C, but can be achieved by a single heat treatment With an e-beam. E-beam-annealed devices have a reverse-bias junction leakage similar to furnace-annealed control samples, and show improvements in short-channel effects such as short-channel threshold voltage shifts and punchthrough, without introducing other deleterious effects. 相似文献
14.
《Electron Devices, IEEE Transactions on》1987,34(1):58-63
The electrical resistivity of TiSi2 formed on polysilicon implanted with phosphorus and arsenic and on n+and p+diffusions implanted with arsenic and boron was measured in the 4.2-300 K temperature range. It is found that in all cases, the resistivity is reduced by a factor of 3-4 when TiSi2 is cooled from room to liquid-nitrogen temperature. Sheet resistance as low as 1 Ω/sq. at liquid-nitrogen temperature can be easily achieved for self-aligned thin TiSi2 layers over polysilicon and diffusion regions, which is very attractive for low-temperature CMOS applications. The residual resistivity ratio, which is a measure of the electron mean free path, decreases with growing surface concentration of dopants, regardless of doping species. The analysis of thickness effects in terms of surface scattering and of grain boundary resistivity models, suggests that degradation of sheet resistance Rs with increased implantation dose is due only partly to the difficulty in forming thick enough TiSi2 at high doses, and that dopant impurities segregated at the grain boundaries can account for the observed increase. 相似文献
15.
The current-voltage (I-V) characteristics of ultrashallow p+ -n and n+-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p+-n junctions were formed by implanting B+ ions into n-type Si (100) at 200 eV and at a dose of 6×1014 cm-2, and n+-p junctions were obtained by implanting As+ ions into p-type (100) Si at 500 eV and at a dose 4×1012 cm-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I -V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm 28Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p+-n and n+-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I -V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10-12 and 2×10-11 A for p+-n and n+-p diodes, respectively, using a junction area of 1.96×10-3 cm2 相似文献
16.
《Electron Device Letters, IEEE》1985,6(9):479-481
Specific contact resistivities of the Al/TiW/TiSi2 /Si system are characterized. It is found that without a TiW barrier layer, Al can penetrate through the TiSi2 layer and significantly affect the TiSi2 /Si interfacial contact resistance. Intrinsic TiSi2 contact resistivities to n+and p+silicon are characterized with a TiW barrier between the silicide and the aluminum. TiSi2 contact resistivity to n+silicon is found to be about one order of magnitude lower than that of Al to n+silicon. However, TiSi2 to p+silicon contact resistivity is higher than that of Al to p+silicon and is very sensitive to the boron implant dose. 相似文献
17.
《Electron Device Letters, IEEE》1987,8(10):483-485
We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p+-n junction. The device was made on a semi-insulating InP substrate with Si++implant for the n-channel and Be/P co-implant for the p+-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 1016/cm3. 相似文献
18.
《Electron Devices, IEEE Transactions on》1981,28(4):374-379
This paper describes the structure and performance of a high-power infrared emitting diode (IRED) designed as a high speed optical beam source for optoelectronic applications. The heterostructured junction is formed on a thick Ga1-x Alx As liquid phase epitaxy (LPE) grown layer which is used to shape hemispherical emitting surfaces. Dislocation density in recombination region was considerably decreased by the thick layer growth on a GaAs wafer used as a primary substrate. Under dc operations, external quantum efficiencies of around 45 percent at a current density of 0.6 kA/cm2and about 110 mW of optical output power at 200 mA (1 kA/cm2) have been obtained from the diodes with a 160-µm junction diameter. The tendency to reach power saturation with increased current has been decreased by means of reducing of thermal resistance of the mount, and the diodes with 240- µm junction diameter have shown about 180 mW at 600 mA dc and 1.4 W at a 4-A pulse (60 Hz, 50 µs). A large improvement in high frequency response has been obtained and the bandwidth at -3-dB intensity has reached above 120 MHz. 相似文献
19.
Bin-Shing Chen Mao-Chieh Chen 《Electron Devices, IEEE Transactions on》1996,43(2):258-266
This work investigates the shallow CoSi2 contacted junctions formed by BF2+ and As+ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p+n junctions fabricated by 20 keV BF2+ implantation to a dose of 5×1015 cm-2, diodes with a leakage current density less than 2 nA/cm2 at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n+p junctions fabricated by 40 keV As+ implantation to a dose of 5×1015 cm-2, diodes with a leakage current density less than 5 nA/cm2 at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As+ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature 相似文献
20.
《Electron Devices, IEEE Transactions on》1985,32(2):203-209
A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+substrate and a retrograde n-well. Self-aligned TiSi2 is formed on n+and p+diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n+poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V. 相似文献