Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Integrated-circuit reliability simulation with emphasis on hot-carrier effects

Reliability assurance and enhancement of analog VLSI circuits are of fundamental importance in the design of high quality signal processing and computing systems. An analog integrated circuit may fial due to degradation of some critical transistors. In this paper, strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. Hot-carrier effects are used to demonstrate the prediction of degradation in circuit performance. This degradation information is propagated through the design hierarchy, with the data at each stage conforming with the complexity of representation at that stage. Circuit topology changes may be made at different levels to reduce the intensive electrical stress applied to weak components. At the top level the chip degradation information is essential for the design of reliable VLSI systems. The method used to include the first-order ac degradation effects into the circuit reliability simulator is described. Experimental results on inverters, precharging circuitry for sense amplifiers, and operational amplifiers designed in submicron technologies are presented.This research was partially supported by National Science Foundation under grant MIP-8710825 and by industrial grants from Samsung Electronics Co. and TRW Inc.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.     

Advanced integrated-circuit reliability simulation includingdynamic stress effects

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented     

Defect tolerance in VLSI circuits: techniques and yield analysis

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit “defect tolerant”, i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits     

Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs

Today's microelectronics researchers design VLSI devices to achieve highly differentiated devices, both in performance and functionality. As VLSI devices become more complex, VLSI device testing becomes more costly and time consuming. The increasing test complexity leads to longer device test programs development time as well as more expensive test systems, and debugging test programs is a great burden to the test programs development. On the other hand, there is little formal theory of debugging, and attempts to develop a methodology of debugging are rare. The aim of the investigation in this paper is to create a theory to support analysis and debugging of VLSI device test programs, and then, on the basis of this theory, design and develop an off-line debugging environment, OLDEVDTP, for the creation, analysis, checking, identifying, error location, and correction of the device test programs off-line from the target VLSI test system, to achieve a dramatic cost and time reduction. In the paper, fuzzy comprehensive evaluation techniques are applied to the program analysis and debugging process to reduce restrictions caused by computational complexity. Analysis, design, and implementation of OLDEVDTP are also addressed in the paper.     

RTD的器件模型和模拟——共振隧穿器件讲座(9)

阐述了电路模拟在设计和研制大规模集成过程中的必要性和重要意义,器件模型在电路模拟中的重要性以及器件模拟与器件模型的关系;在器件模拟通用软件形成过程的基础上重点讨论了RTD的器件模型、器件模拟和电路模拟软件SPICE三个课题;介绍了基于物理参数I-V方程RTD模型和高斯函数、指数函数RTD直流模型;利用ATLAS器件模拟通用软件对RTD进行了器件模拟,得到了势垒和势阱宽度、E区掺杂浓度等对RTDI-V特性的影响;以包含RTD电路的SPICE电路模拟中的文字逻辑门为例,通过电路模拟验证了其逻辑功能,对设计该电路起到指导和参考作用。     

Circuit development using biological components: Principles, models and experimental feasibility

Today most VLSI circuits are built in silicon using CMOS transistors. Developments in design automation and process fabrication have resulted in the progressive increase of the number of transistors per chip and decrease in the size of the transistors. But transistor designers are fast approaching fundamental physical barriers to further size reduction. Thus engineers are looking at alternate technologies such as nano-devices and bio-circuits for next-generation circuits. In our research, we concentrate on the development of bio-circuits and their applications. Our eventual goal is the design and simulation of complete systems integrating bio-circuits and VLSI technology appropriately. Bio-circuits are circuits developed in vivo or in vitro, using DNA and proteins. A biological process such as glycolysis or bioluminescence can be viewed as a genetic regulatory circuit, a complex set of bio-chemical reactions regulating the behavior of genes, operons, DNA, RNA, and proteins. Similar to voltage in an electrical circuit, a genetic regulatory circuit produces an output protein in response to an input stimulus. We can engineer bio-circuits to meet design specifications, using genetic engineering. Our aim is to build a library of in vitro bio-circuits representing the Boolean functions. The bio-circuits from this library can be further cascaded to form larger circuits. In this paper, we review the feasibility of building bio-circuits. We discuss the construction of Boolean logic gates such as NOT, AND, and OR and their verification by simulation. We also address important aspects such as cascading of the bio-circuits and practical implementation. In addition, we describe an algorithm “Box” that can help to control bio-circuit characteristics such as gain and switching behavior. This approach is similar to design space exploration in traditional VLSI, but takes into account biological knowledge obtained through experiments. We also provide insight into the robustness of bio-circuits in the presence of noise. This paper is intended to pave the pathway for electrical engineers to start exploring the field of bio-circuits.     

A process simulation model for multilayer structures involving polycrystalline silicon

The increasing complexity of VLSI fabrication often requires the use of multilayer structures above the silicon substrate. Electrical and metallurgical properties of multilayer structures have an important effect on circuit performance and reliability. Although process simulation models are available and widely used for computer-aided process design, none of the existing process simulation programs have the capability for modeling multilayer structures. A new model with such capability has been developed and this paper presents the physics as well as the results of simulation supported by experimental data. The model can simulate many desirable properties of multilayer structures involving polycrystalline silicon, such as grain growth, resistivity and oxidation rate of the polysilicon layer, the impurity redistribution across multilayers after high-temperature thermal processing, impurity segregation both at grain boundaries and at interfaces, and the interdependent phenomena of dopant-dependent oxidation/diffusion.     

Progress in the methodologies for the electrical modeling ofinterconnects and electronic packages

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems     

一款通用CPU中的Load Aligner数据通道的全定制设计

深亚微米时 ,芯片的设计和制造成了一个复杂浩大的工程体系。本文以一款通用CPU的LoadAligner数据通道部分的全定制设计为例 ,讲述了一个集成电路子模块的逻辑设计 ,电路设计 ,版图设计 ,并给出了相关结果     

A 32-Bit Custom VLSI Processor for Communications Network Nodes

Aimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardware simulators efficiently eliminated logic errors. Microprogram control memory is placed externally to VLSI chips to facilitate tentative correction of possible remaining errors. Two types of processors sharing uniform architecture were also developed for an overall optimum cost-effectiveness using these VLSI chips. One uses all three kinds of VLSI chips and is suitable for switching and communications processing applications. The other includes one VLSI chip and consists of a single printed circuit board. It is suitable for a portable console processor or a processor imbedded in various equipment. These VLSI processors are being introduced in large numbers in communications networks in Japan.     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models