H.264解码器的ASIC解决方案及其FPGA验证平台

论述了H.264解码器的ASIC(专用芯片)解决方案及其FPGA验证平台.该方案比常见DSP解决方案有更快的解码速度和更低的能耗,解决了H.264解码器由于算法复杂性增大带来的速度和能耗问题.鉴于大规模SoC芯片验证的复杂性,还比较详细地介绍了该芯片基于FPGA的验证平台.     

H.264解码芯片的比较与研究

介绍了H.264解码芯片的发展状况,对比了现在主流的几种解码方案,总结出各种编码方案的优缺点,并根据解码芯片的发展状况,分析了TI公司的达芬奇DM644X系列DSP的结构,对该系列产品的开发特点作了简单的总结.     

IC与半导体

NEC机顶盒用系统芯片集成新一代视频标准H.264解码功能NEC电子日前完成了2款适用于中国、欧洲、俄罗斯、印度、巴西等地区的系统芯片方案,支持H.264视频标准的机顶盒系统的开发,以EMMA3SL/HD、EMMA3SL/SD的产品名于即日     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

基于S3C6410的实时视频监控系统

介绍了基于ARM微处理器S3C6410的嵌入式视频服务器硬件、软件设计方案.该方案以嵌入式Linux作为操作系统,采用S3C6410自带的编码器MFC对采集到的数字视频进行H.264标准的压缩编码,生成H.264码流.码流经过S3C6410控制器外接的网络芯片DM9000输送到PC机.PC机使用DirectShow技术解码H.264码流,并实现实时视频播放.     

H.264视频解码芯片中与滤波相关的存储器的设计

本文对H.264解码芯片中的滤波部分所需的数据、数据的存取及芯片中所用到的存储器做了深入的分析,同时涉及到DRAM及SRAM的设计,并支持宏块级帧场自适应。为了实现H.264解码芯片中的数据的快速存取,本文提出了对数据存储的一种优化方法,通过此方法可完全达到滤波过程中对大量数据的处理。试验表明此种方法能节约存储器的资源并满足H.264滤波中对大数据量处理的需求。     

H.264视频解码器芯片中与滤波相关的存储器的设计

本文对H.264解码芯片中的滤波部分所需的数据、数据的存取及芯片中所用到的存储器做了深入的分析,同时涉及到DRAM及SRAM的设计,并支持宏块级帧场自适应.为了实现H.264解码芯片中的数据的快速存取,本文提出了对数据存储的一种优化方法,通过此方法可完全达到滤波过程中对大量数据的处理.试验表明此种方法能节约存 储器的资源并满足H.264滤波中对大数据量处理的需求.     

H.264硬件解码核的FPGA实现

针对H.264/AVC的视频解码问题进行了研究,给出了H.264解码核的硬件实现方案,对熵解码CAVLC查表方案进行了优化.详细介绍了句法预测模块、反量化、逆DCT以及帧内预测模块的具体实现结构;并引入流水线、并行处理和状态机处理方法来提高处理速度,实现了解码结构上的优化.该算法在EP2S60F672C5ES FPGA上获得验证,结果表明给出的H.264解码算法是正确的,且有节省硬件资源和较快解码速度的优点.     

H.264视频解码芯片中视频控制器的设计

本文介绍了应用于H.264解码专用芯片的视频控制器模块的设计方法,详细分析了其工作原理和设计思想,以及设计中的一些特殊技术。该模块实现了YUV转RGB信号的色度空间转换,并通过重采样实现了对原始视频图像的整数、分数的格式转换。采用该模块的H.264解码专用芯片可以应用于液晶电视和需要数字图像缩放的各类显示屏中。     

H.264解码器的系统设计及CAVLC的硬件实现

设计了一种软硬件协同处理的H.264解码器系统方案,基于该方案给出CAVLC解码模块的硬件实现结构,采用有限状态机实现解码的流程控制,并对其查表部分进行优化.验证结果表明,在尽量降低硬件资源损耗的基础上,该方案能满足H.264基本框架4CIF格式图片30 f/s(帧/秒)实时解码的要求.     

H.264/AVC解码器芯片应用简介

介绍了目前市场上一些主流的支持H．264视频解码的芯片，比较了他们的特性和应用，并简述了自行开发的应用于移动视频领域的H．264视频芯片，指出了移动视频芯片开发的必要性和今后发展趋势。     

基于H.264 SVC无线视频传输的自适应差错保护方法

提出了一种针对H.264可分级编码(H.264 SVC)的自适应前向纠错编码保护方案.通过比较不同的纠错方案,提出了划分丢包率区间的概念,并根据不同区间的丢包率自适应地选择最佳的纠错方案.仿真结果表明,与单一保护方法相比,所提自适应方法能够取得更好的保护效果,更适于在无线信道中进行视频传输.     

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.     

Hardware design of motion data decoding process for H.264/AVC

In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor’s Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW.     

Perceptually driven video error protection using a distributed source coding approach

In video communication systems, the video signals are typically compressed and sent to the decoder through an error-prone transmission channel that may corrupt the compressed signal, causing the degradation of the final decoded video quality. In this context, it is possible to enhance the error resilience of typical predictive video coding schemes using as inspiration principles and tools from an alternative video coding approach, the so-called Distributed Video Coding (DVC), based on the Distributed Source Coding (DSC) theory. Further improvements in the decoded video quality after error-prone transmission may also be obtained by considering the perceptual relevance of the video content, as distortions occurring in different regions of a picture have a different impact on the user's final experience. In this context, this paper proposes a Perceptually Driven Error Protection (PDEP) video coding solution that enhances the error resilience of a state-of-the-art H.264/AVC predictive video codec using DSC principles and perceptual considerations. To increase the H.264/AVC error resilience performance, the main technical novelties brought by the proposed video coding solution are: (i) design of an improved compressed domain perceptual classification mechanism; (ii) design of an improved transcoding tool for the DSC-based protection mechanism; and (iii) integration of a perceptual classification mechanism in an H.264/AVC compliant codec with a DSC-based error protection mechanism. The performance results obtained show that the proposed PDEP video codec provides a better performing alternative to traditional error protection video coding schemes, notably Forward Error Correction (FEC)-based schemes.     

H.264的几种抗误码方法的分析与比较

从较新的视频压缩编码标准H.264出发,并结合Internet信道包丢失模型,对几种在编码端常用的抗误码方法进行了分析和比较。实验证明,在实际的Internet信道误码环境下,全局率失真优化的编码模式判决方法具有较强的错误鲁棒性和实用性。     

A new bandwidth allocation mechanism for next generation wireless cellular networks

In this paper we design and study the performance of a Medium Access Control (MAC) scheme for the multiplexing and the integrated delivery of voice, mobile messaging, IP, gaming and H.264 videoconference traffic over a high-speed cellular TDMA channel with errors and capture. To the best of our knowledge, this is one of the first papers in the literature investigating the integration of actual H.264 video traces and gaming traffic with other types of traffic over wireless networks. Our results show that the proposed scheme achieves high throughput results while preserving the strict Quality of Service (QoS) requirements of each traffic type, and outperforms two efficient schemes previously proposed in the literature.     

Data and gate line sharing methods for low-cost and high-pixel density TFT-LCDs

New pixel circuit and driving schemes to reduce the number of both data lines and gate lines to half of the traditional TFT-LCDs are proposed. This idea contributes to cost-down of TFT-LCDs by halving the number of the required data driver ICs and gate driver ICs and supports higher-resolution TFT-LCDs by doubling the pitch of data lines.     

Rate control for hierarchical B-frames in H.264/AVC

Hierarchical B-frames can bring high coding performance when introduced into H.264/AVC.However,the traditional rate control schemes can not work efficiently in such new coding framework.This article presents a rate control algorithm for hierarchical B-frames in H.264/AVC.Taking the feature of the dyadic hierarchical coding structure into consideration,the proposed algorithm includes group of pictures(GOP)layer,temporal layer and frame layer bits allocation.After frame layer bits allocation is complete,frame layer quantization parameters(QP)determination strategy is responsible for calculating the final QP.Experimental results show that compared with other rate control algorithms,the proposed one can improve the coding performance and reduce the mismatch of target bit rate and real bit rate.     

Robust multipoint and multi-layered transmission of H.264/SVC with Raptor codes

The scalable extension of the H.264 Advanced Video Coding (AVC) standard called Scalable Video Coding (SVC), or H.264/SVC, provides scalable video streams which are composed by a base layer and one or more enhancement layers. Enhancement layers may improve the temporal, the spatial or the signal-to-noise ratio resolutions of the content represented by the lower layers. One of the applications of this video coding standard is related to point-to-multipoint video distributions in both wired and wireless communication systems, where packet losses contribute to the degradation of the user’s Quality of Experience. Designed for the transmission of data over Binary Erasure Channels (BEC), Raptor codes are a Forward Error Correction (FEC) mechanism that is gaining popularity for Internet Protocol Television (IPTV) applications due to their small decoding complexity and reduced overhead. This paper evaluates the quality enhancements introduced by the integration of several H.264/SVC layers with a Raptor coding protection scheme. Our goal is to improve the distribution of video over loss prone networks in terms of rate-distortion performance by assessing several alternative packetization options and protection schemes.