4 Gbit/s receiver with adaptive blind DFE

A serial backplane receiver with adaptive blind decision feedback equalisation (DFE) is proposed, which can operate at up to 4 Gbit/s over 1.2 m distance, which includes discontinuities due to the packaging and backplane connectors. A reduced complexity DFE implementation is achieved by biasing high-speed comparators. DFE coefficient calculation is not performed on every consecutive received sample, which significantly reduces the design complexity and power consumption.     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

0.18 /spl mu/m CMOS backplane receiver with decision-feedback equalisation embedded

Decision-feedback equalisation (DFE) is explored to reduce intersymbol interference and crosstalks in high-speed backplane applications. In the design of the clock and data recovery circuit, embedding DFE within a phase and frequency detector enhances the recovery of data inherently from distorted input signals and facilitates providing DFE with the recovered clock.     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10⁻⁹. The total active area is 0.21 mm² and the ADC consumes 76 mW from a 1.2-V supply.     

一种高速大容量背板的设计与实现

背板是通信设备的要求.采用传统的板卡平行连接结构的背板,要继续增加带宽已经非常困难,从而成为制约系统容量的一个瓶颈.本文给出了一种采用前后交叉连接结构的高速大容量背板的具体设计实现,在保证信号完整性前提下大大降低了设计难度,其总带宽达到1Tb/s.     

Physical design issues for very large ATM switching systems

The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed     

Bi-directional optical backplane bus for general purposemulti-processor board-to-board optoelectronic interconnects

We report for the first time a bidirectional optical backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8×9) cascaded fanouts, are generated. Data transfer of 1.2 Gbt/s at 1.3-μm wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as transceiver size and misalignment are embarked upon to provide a reliable system with a wide bandwidth coverage. Theoretical treatment to minimize intensity fluctuations among the nine modules in both directions is further presented and an optimum design rule is provided. The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE standardized buses as VMEbus, Futurebus and FASTBUS, and can function as a backplane bus in existing computing environments     

FPGA GTP技术在光传输设备背板总线的应用

对目前通用的光传输设备背板总线传输的方法进行了分析,针对该方法的不足提出了一种应用FPGA GTP技术完成光传输设备背板总线传输的方式.详细介绍了FPGA GTP技术的优势和特点,并对FPGA GTP进行了合理的软、硬件设计,实现了在光传输设备背板中不同业务、不同速率的混合总线的串行传输.     

Adaptive combined DFE/MLSE techniques for ISI channels

By embedding a decision-feedback equalizer (DFE) into the structure of a maximum-likelihood sequence estimator (MLSE), an adaptive combined DFE/MLSE scheme is proposed. In this combined DFE/MLSE, the embedded DFE has three functions: (i) prefiltering the received signals and truncating the equivalent channel response into the desired one, (ii) compensating for channel distortions, and (iii) providing the MLSE detector with predicted values of input signals. Since the embedded MLSE detector operates on the predicted signals the detected symbols at the output of the DFE/MLSE do not suffer any delay and can be directly fed back into the embedded DFE so that the error propagation, which usually takes place in a conventional DFE, can be greatly reduced. Analytical and simulation results indicate that the performance is significantly improved by the DFE/MLSE compared to the conventional DFE while its computation complexity is much less than that of the conventional MLSE receiver. The combined DFE/MLSE can use different adaptive structures (block-updating, sliding window updating or symbol-by-symbol updating) to meet different performance objectives. Moreover, the proposed DFE/MLSE provides a trade-off between performance and complexity with a parameter m representing the MLSE detection depth as well as the number of predicting steps of the embedded DFE. For some particular values of m, this scheme is capable of emulating the conventional DFE, MLSE-VA, adaptive LE-MLSE equalizer, adaptive DDFSE, and adaptive BDFE without detection delay     

Decision feedback equaliser design using support vector machines

The conventional decision feedback equaliser (DFE) that employs a linear combination of channel observations and past decisions is considered. The design of this class of DFE is to construct a hyperplane that separates the different signal classes. It is well known that the popular minimum mean square error (MMSE) design is generally not the optimal minimum bit error rate (MBER) solution. A strategy is proposed for designing the DFE based on support vector machines (SVMs). The SVM design achieves asymptotically the MBER solution and is superior in performance to the usual MMSE solution. Unlike the exact MBER solution, this SVM solution can be computed very efficiently     

Optimized decision-feedback equalization for convolutional coding with reduced delay

Error propagation is a significant problem with the decision-feedback equalizer (DFE) at low-to-moderate signal-to-noise ratios. In particular, when a DFE is concatenated with a convolutional code, the burst errors associated with error propagation can severely degrade performance, since the convolutional code is optimized for the additive white Gaussian noise channel. In this paper, we explore the compensation of error propagation in the DFE so as to break up error bursts and improve performance with convolutional codes, without incurring larger overall decoding delay. We propose certain stationary error models and derive a modified DFE (MDFE) based on these models which can compensate for the error propagation. The MDFE differs from the conventional DFE only in its tap values. The incorporation of the bias into the model and the removal of the bias during the design process is discussed. Simulations explore the performance of the MDFE for both uncoded and convolutionally coded systems. With coding, the MDFE can significantly improve on the conventional DFE in terms of bit-error rate, and the MDFE without interleaving can improve on the conventional DFE with interleaving in terms of decision delay.     

High speed serial transceivers for data communication systems

The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards     

A mixed-signal decision-feedback equalizer that uses a look-aheadarchitecture

A mixed-signal decision-feedback equalizer (DFE) that uses a look-ahead architecture is described. The parallelism in the look-ahead DFE (LA DFE) achieves an increase in the data rate over a conventional DFE with a small increase in area. Fully differential analog circuits perform the convolution operation in the LA DFE, and the coefficient adaption is carried out by digital circuits. The LA DFE occupies 23 mm ² in a 2-μm CMOS process and operates at 50 Mb/s while dissipating 260 mW     

Mitigating error propagation effects in a decision feedbackequalizer

We present an approximate analysis approach to the computation of the probability of error and mean burst error length for a decision feedback equalizer (DFE) that takes into account feedback of decision errors. The method uses a reduced-state Markov model of the feedback process and is applicable to linear modulation formats. We use this technique to analyze a DFE design that mitigates the effects of feedback error by incorporating a soft decision device into the feedback path and a norm constraint on the feedback filter weights. We apply the DFE design and analysis approach to a dispersive multipath propagation environment     

Asymptotic Bayesian decision feedback equalizer using a set of hyperplanes

We present a signal space partitioning technique for realizing the optimal Bayesian decision feedback equalizer (DFE). It is known that when the signal-to-noise ratio (SNR) tends to infinity, the decision boundary of the Bayesian DFE is asymptotically piecewise linear and consists of several hyperplanes. The proposed technique determines these hyperplanes explicitly and uses them to partition the observation signal space. The resulting equalizer is made up of a set of parallel linear discriminant functions and a Boolean mapper. Unlike the existing signal space partitioning technique of Kim and Moon (1998), which involves complex combinatorial search and optimization in design, our design procedure is simple and straightforward, and guarantees to achieve the asymptotic Bayesian DFE.     

High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems

This brief addresses the design of a decision feedback equalizer (DFE) for gigabit throughput rate. It is well known that the feedback loop in a DFE limits an upper bound of the achievable speed. For a$L$-tap feedbackward filter (FBF) and$M$-pulse amplitude modulation, Parhi (1991) and Kasturia and Winters (1991) reformulated the FBF as a$(M) ^L$-to-1 multiplexer. Due to the reformulation, the overhead of extra adders and extra multiplexers are as large as$(M) ^L$. The required hardware overhead should be more severe when the DFE is implemented in parallel. In this brief, we propose two new approaches to implement the DFE when gigabit throughput rate is desired. The first approach is partial pre-computation scheme, which can trade-off between hardware complexity and computational speed. The second approach is two-stage pre-computation scheme, which can be applied to higher speed applications. In the later case, we can reduce the hardware overhead to about$2(M) ^(-L/2)$times of , , and the iteration bound is$(log _2 W+2)/(L/2+1)+(log _2 M)$multiplexer-delays, where$W$is the wordlength of weight coefficient of a FBF. We demonstrate the proposed architectures by apply it to the 10 Gbase-LX4 optical communication systems.     

ADM4210热插拔控制器的原理及应用

ADM4210器件构成的热插拔保护电路,为电路提供欠压、过压、过流和短路保护,能够在不响应工作底板正常运行情况下．实现板卡的热插拔。介绍了ADM4210的主要特性、工作原理及应用电路设计。     

A method for rebroadcasting signals in an optical backplane bussystem

A guided-wave optical backplane bus system intended for use in high-performance board-to-board interconnects is described. Its multiplexed polymeric holograms can implement optical signal broadcast between boards so that all boards share common optical channels. By introducing an active coupler to the doubly multiplexed hologram at the center board, signals received from any board can be rebroadcast to all other boards. We describe the design concepts for a centralized optical backplane and the resulting performance and assembly advantages over previously developed guided-wave and free-space optical backplane bus systems used for broadcasting signals. These advantages include equalized fan-out power, increased interconnect distance, and simpler fabrication