Design of a FASTBUS Programmable Sequencer Module and Memory Module

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.     

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.     

Real Time Diagnostic Data Acquisition System for the Doublet III Tokamak Fusion Experiment

The Doublet III data acquisition computer system acquires, archives, and processes over three megabytes of data from each shot of the experiment. A shot lasts 1-2 seconds and occurs every 5-6 minutes with 50-100 shots/day. The data acquisition system has been configured to efficiently handle the increasing quantity of data as new plasma instruments are added (five megabytes within a year) and to provide interactive capability during operations. The configuration is a dual CPU system with a dual port disk and bulk core memory. One CPU is devoted to acquisition and archiving while the other CPU is for analysis and interactive use. This system has enabled improved shot-to-shot processing of plasma data thus providing guidance to the physics operations team. A planned upgrade of Doublet III will require data handling of over 20 megabytes/ shot.     

FASTBUS—CAMAC数据采集系统在宇宙线EAS实验中的应用

本文以中日合作西藏羊八井宇宙线ＥＡＳ实验所使用的ＦＡＳＴＢＵＳ－ＣＡＭＡＣ混合数据采集系统为例，介绍了ＦＡＳＴＢＵＳ总线的主要特点，功能模块、控制模块以及与ＰＣ的接口功能和控制方法，并对ＦＡＳＴＢＵＳ的具体应用进行了深入的分析。     

A DSP based FASTBUS board for data acquisition or high leveltrigger control in DELPHI electromagnetic calorimeters

A versatile FASTBUS board that is based on fast digital signal processors (DSPs) and analog-to-digital converters is described. It has been developed for the real-time acquisition and online processing of signals produced in different electromagnetic calorimeters of the DELPHI detector at the LEP (Large Electron Positron) collider. The board contains six TMS32010 DSPs, six piggyback cards for the analog-to-digital conversion, a set of 512-word FIFO memories for data exchange between contiguous DSPs and with external devices and a 16 K×16 random-access memory for data storage, accessible both to the DSPs and to FASTBUS in an asynchronous way, with override privilege granted to the DSPs     

A dual-port FASTBUS memory to test the L3 data acquisition system

A dual-port 0.25-Mbytes (64 K×32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and read operations, respectively. The memory, successfully used to test the L3 event builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large data acquisition systems     

FASTBUS State Generator a Simple, High Speed Module for Testing FASTBUS Interfaces

The FASTBUS State Generator provides a convenient method of independently controlling FASTBUS signals at normal bus speeds. Parallel generation or test of all FASTBUS lines at rates up to 25 MHz is possible using a simplified version of BASIC. The module may be programmed to emulate many of the sequential interface charateristics of standard FASTBUS devices     

The 3081/E Processor and Its on-Line Use

The 3081/E is a second generation emulator of a mainframe IBM. One of it's applications will be to form part of the data acquisition system of the upgraded Mark II detector for data taking at the SLAC linear collider. Since the processor does not have direct connections to I/O devices a FASTBUS interface will be provided to allow communication with both SLAC Scanner Processors (which are responsible for the accumulation of data at a crate level) and the experiment's VAX 8600 mainframe. The 3081/E's will supply a significant amount of on-line computing power to the experiment (a single 3081/E is equivalent to 4-5 VAX 11/780'S). A major advantage of the 3081/E is that program development can be done on an IBM mainframe (such as the one used for off-line analysis) which gives the programmer access to a full range of debugging tools. The processor's performance can be continually monitored by comparison of the results obtained using it to those given when the same program is run on an IBM computer.     

A dual-parameter multichannel analyzer by a dual-computer system

The design and feasibility of a simple and practical system for measuring two-parameter signals is reported. A dual-parameter multichannel pulse-height analyzer (MCA) which uses two central processing units (CPUs) is developed and designed. One computer (master computer) controls the other computer (slave computer), and also displays, records, and analyzes the data. The slave computer controls two analog-to-digital converters (ADCs), collects the dual-parameter data, and transfers the collected data to the master computer. Three methods of data transfer between the two CPUs are examined and discussed. The count capacity at the data collection by the slave computer is 2¹⁶-1/ch (2-B-long data), and this is expanded to 2³²-a/ch (4-B-long data) at the master computer. The data are analyzed and at any time stored in the storage apparatus by the dual CPU system. The system demonstrates stable operation over long measurement periods     

A multi-function FASTBUS front-end for VAXBI computers

A versatile and high-performance interface between DEC computers based on VAXBI and FASTBUS has been designed to couple a general-purpose FASTBUS master with a specially developed intelligent module. The hardware capabilities of the interface are discussed, with particular reference to the Aleph event builder (AEB), which is a single-width FASTBUS card based on the MC68020 CPU and the MC68881 floating-point coprocessor, and the AEB-VAX interface. The software, as implemented in the Aleph experiment at the LEP (Large Electron Position) collider, is presented, covering the communication protocol, the software for the high-speed interface to the DEC DRB32 BI adapter, the AEB software, and the VAX software. The results of a performance evaluation for single-word and block transfer actions are presented     

A high speed, fibre optic, link for Digital Equipment CorporationVAXes

The authors describe an optical fiber link that is used in conjunction with the CERN host interface family to connect high-performance VAXes to VMEbus or FASTBUS over distances up to 1000 m. The modular construction allows other permutations, including VAX/VAX, FASTBUS/FASTBUS, VMEbus/VMEbus, or FASTBUS/VMEbus connections, over similar distances. The link comprises two identical optical data interconnects (ODI) connected by two unidirectional multimode fibers. The ODI at each end of the link can be connected to any device conforming to the DRB32 user interface specification. The authors discuss the operation of an ODI, the testing of the optical link, and present and future ODI implementations     

FASTBUS Cable Segment Extender Based on TTL

A method to drive a FASTBUS cable segment over long distance is described. The signal level transmitted is converted from standard FASTBUS cable segment signal to a TTL differential output; the scheme increases noise immunity. In addition, the receiver has a wide tolerance of common mode range of +/-15 V. By applying a deskewing mechanism in the extender module, we have achieved more than 1010 transactions of FASTBUS without any error with a cable length of 100 m.     

A High Speed Data Acquisition System for Fermilab Experiments

A high rate data acquisition system has been used to record some 40 million complex events in an experiment studying the hadroproduction of charm in Fermilab's Broad Band Neutral Beam. Event data is accumulated during the spill in large buffer memories without computer intervention through the University of Illinois Black Bin System. Between spills the memories are read by their FASTBUS ports to a PDP-11/45 for recording on magnetic tape. A sample of events is held for analysis by the program MULTI during the following spill.     

FASTBUS Implementation Review

For the last few years, enough has been known about the properties and capabilities of FASTBUS for it to be incorporated into the design of some experiments. As a result, despite the newness of the specification, a number of systems using FASTBUS are well advanced and a few even completed. We discuss some of these systems from several viewpoints, including why FASTBUS was chosen, how painful was the implementation and the role played by the software. FASTBUS systems in the United States, Europe and Japan are included in this review.     

The FASTBUS Segment Interconnect

The FASTBUS Segment Interconnect provides a communication path between two otherwise independent, asynchronous bus segments. In particular, the segment interconnect links a backplace (crate) segment to a cable segment. All standard FASTBUS address and data transactions can be passed through the SI, or any number of SI's and segments in a path. Thus systems of arbitrary connection complexity can be formed, allowing simultaneous independent processing, yet still permitting devices associated with one segment to be accessed from others. The model S1 segment interconnect being built at the University of Illinois supports these and other important features.     

高速VME—FASTBUS接口系统

本文介绍一种新型高速ＶＭＥ－ＦＡＳＴＢＵ接口系统，系统包括一个基于ＭＣ６８０４０处理器的ＦＡＳＴＢＵ控制器，一个ＶＭＥ双端口存储器插件和相应的软件，最后给出了测试结果。     

快总线——新一代的高速数据获取和控制总线系统

快总线由机箱相电缆两种总线段互连而成。每一个段都是一个有自治能力的单元,可容纳多个处理机,段的操作完全是并行独立的。本文介绍快总线的发展和现状,并讨论了它的基本原理和操作。