A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

Process-induced and environmental fluctuations play an important role in the design process for modern high-performance integrated circuits. The conventional principle of considering the verification of worst-case requirements reduces the performance that can potentially be achieved by circuits and technology. This paper presents a new mechanism that permits the compensation of random independent delay fluctuations due to environmental factors. It shows that it is significantly possible to reduce the latency time of a circuit even for a moderate length of pipeline stages.     

C/SUP 2/L: A new high-speed high-density bulk CMOS technology

C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS).     

A new leakage mechanism of Co salicide and optimized processconditions [for CMOS]

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-μm CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi_x spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi_x spikes grow rapidly only during annealing between 400 and 450°C for 30 s when Co₂Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850°C for 30 s. This is because a trade-off exists between reducing the CoSi_x spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C     

Modeling device isolation in high-density CMOS

Extensive two-dimensional (2-D) modeling has been performed to study device isolation in high density CMOS. Isolation breakdown mechanisms consisting of surface inversion and lateral punchthrough have been analyzed for various isolation spacings between an n- and a p-channel transistor. The modeling results suggest that through a careful process and device design, adequate device isolation can be achieved for a 2-µm n+-to-p+ spacing using conventional field isolation.     

A new on-chip converter for submicrometer high-density DRAMs

The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAMs with submicrometer transistors.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

A new compact CMOS C-multiplier

This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the translinear principle with MOSFETs operating in subthreshold region. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator was used to confirm the functionality of the design in 0.18 µm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor can be varied from 10 to 300. The functionality of the proposed capacitance multiplier was demonstrated by using it in designing a low pass filter and a relaxation oscillator.     

A new self-aligned well-isolation technique for CMOS devices

This paper presents the development of a new well-isolation technique for advanced CMOS LSI's. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.     

A new CR-delay circuit technology for high-density and high-speedDRAMs

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved     

A new high-density fiber organizer for optical-fiber cable joints

A new slack fiber organizer structure composed of individual box-shaped plastic sheets is presented. It is capable of accommodating 800 fiber splices with the same size as the existing metallic cable joints. The conditions to accommodate reinforced mass-splices and slack fibers into the organizer are clarified by considering optical loss increase and reliability evaluation for bent fiber ribbons, and also a computer-aided dimension simulation. The new organizer with 800 fiber splices experimentally exhibits good transmission characteristics with an average slack fiber accommodation loss of 0.04 dB and a good workability of 1.2 min/ribbon.     

A high-density conduction-based micro-DNA identification array fabricated with a CMOS compatible process

A high-density CMOS-compatible deoxyribonucleic acid (DNA) array fabricated with a modified metallization process is demonstrated. The array consists of silicon nitride isolation to confine the DNA sample to a specific cell area defined by silicon dioxide to achieve low crosstalk between neighboring cells. A prehybridization process together with a conductive enhancement method are also developed to improve the signal to noise ratio. Nine orders of magnitude difference in conductance is measured between array cells with matched and single-based mismatched DNA samples. The matching of DNA molecules can then be easily detected by a simple digital switching circuit.     

A new buried-oxide isolation for high-speed high-density MOS integrated circuits

The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices.     

CMOS图像传感器新技术——C^3D

C3D(CMOS Color Captive Device)是新一代半导体成像技术,它不仅提高了像素设计技术,也改进了生产工艺.采用这种技术生产的0.25 μ mCMOS图像传感器能够在不牺牲性能的前提下增加晶体管的数量和占空因数(Fill Factor).除了增加像素设计的选择方案之外,还可实现更为复杂的功能和更低的功耗,并且在速度方面也很有优势.     

A new fuzzy-based decision algorithm for high-density impulse noise removal

This paper proposes a new efficient fuzzy-based decision algorithm (FBDA) for the restoration of images that are corrupted with high density of impulse noises. FBDA is a fuzzy-based switching median filter in which the filtering is applied only to corrupted pixels in the image while the uncorrupted pixels are left unchanged. The proposed algorithm computes the difference measure for each pixel based on the central pixel (corrupted pixel) in a selected window and then calculates the membership value for each pixel based on the highest difference. The algorithm then eliminates those pixels from the window with very high and very low membership values, which might represent the impulse noises. Median filter is then applied to the remaining pixels in the window to get the restored value for the current pixel position. The proposed algorithm produces excellent results compared to conventional method such as standard median filter (SMF) as well as some advanced techniques such as adaptive median filters (AMF), efficient decision-based algorithm (EDBA), improved efficient decision-based algorithm (IDBA) and boundary discriminative noise detection (BDND) switching median filter. The efficiency of the proposed algorithm is evaluated using different standard images. From experimental analysis, it has been found that FBDA produces better results in terms of both quantitative measures such as PSNR, SSIM, IEF and qualitative measures such as Image Quality Index (IQI).     

A mechanism for asymmetric data writing failure

As dynamic random access memory (DRAM) technology develops further, it is more difficult to sustain a sufficient sensing margin to detect weak cell data. Therefore, a high data writing performance is necessary in order to guarantee the data sensing margin. In this paper, an analysis of the phenomenon of an asymmetric data writing failure (ADWF) is presented, taking account of a bit line sense amplifier (BLSA) offset, and the failure mechanism has been studied through the use of measurement analysis.     

A new high-density low-voltage SSIMOS EEPROM cell

An efficient low-voltage EEPROM cell is described which occupies an area of 135 µm²when fabricated with 3-µm CMOS technology. To charge and discharge the floating gate, the device relies on Fowler-Nordheim tunneling of electrons between the floating gate and a narrow window of the device channel region. In addition, the control gate is positioned so as to shield the remaining portion of the floating gate from the substrate. The cell can be programmed in 10 ms with a nominal WRITE voltage of 16 V and an ERASE voltage of 12 V. The WRITE/ERASE endurance of the cell is in excess of 10⁶cycles, and the data retention has been shown to be greater than 10 years at 125°C.     

Modeling neutron ionization effects on high-density CMOS circuit elements

The mechanisms are analyzed of the action of neutrons on high-density CMOS circuit elements. A procedure is proposed for calculating the single-event-upset and single-hard-error cross sections of CMOS memory cells exposed to neutrons.     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A new design topology for low-voltage CMOS current feedback amplifiers

A new topology for designing low-voltage current feedback amplifiers (CFAs) is presented. By employing a second-generation positive current conveyor followed by an operational amplifier in an unconventional manner, the design circumvents the problem of trying to achieve large transimpedance in a low-voltage environment. It is shown that this CFA configuration also results in near gain independent closed-loop bandwidth defined by a single feedback resistor. The proposed amplifier was verified experimentally by a chip designed using Taiwan Semiconductor Manufacturing Company's 0.18-/spl mu/m digital CMOS process of a single-ended power supply of 1.8 V.     

A new criterion for transient latchup analysis in bulk CMOS

A criterion for transient latchup of p-n-p-n structures initiated by current pulses is described. Based on the circuit-orient model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that the large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents