具有自校准功能的多通道数字下变频器设计

针对多通道通信雷达系统中下变频器件功能单一及幅相校准电路实现复杂的问题，采用多模式全流水线坐标旋转数字计算机设计了一种改进的全数字下变频电路。改进的设计在输入端利用其旋转模式实现数字下变频功能，在基带端利用其向量模式计算通道幅相误差并形成反馈补偿，具有精简的硬件系统结构。闭环实验结果表面，系统自校准后的基带幅度误差控制在0.08dB内，相位误差控制在0.15°内，进一步验证了提出方法的可行性和正确性。     

干涉SAR模拟器通道幅相特性实时校正方法

干涉SAR模拟器是构建单航过InSAR系统地面半实物仿真系统的重要地检设备,模拟器通道幅相非理想特性会影响对干涉性能的准确评估.研究了基于实时滤波校正模拟器通道幅相特性的方法:采用相关加窗处理从闭环数据中提取通道幅相特性,提出了复Remez算法和遗传算法相结合的方法设计复FIR滤波器系数,采用FPGA实现高数据率数据的实时滤波.通过实时校正将模拟器通道间幅相一致性误差峰峰值从1 dB/10度量级提高至0.1 dB/1度水平,半实物试验验证了本文实时校正方法的有效性.     

一种雷达数字中频接收机处理方法与实现

提出了和、差三通道雷达数字中频接收机的一种处理方法.该方法采用数字下变频将中频信号转换为正交视频信号,使用数字自动增益控制提高接收机的动态范围,通过相参积累和数字鉴频提取多普勒频率,根据和、差比幅提取方位和俯仰角误差,并以调节差通道本振初相的方式实现和、差通道幅相一致性校正.给出了用单片现场可编程门阵列实现数字中频接收机处理的具体方法.通过对接收机的实际测试表明,处理测量精度满足系统要求.     

大时带积线性调频信号源幅相误差分析与校正

针对产生LFM信号的数字方法，分析了系统的幅相误差来源，并根据误差频率对其进行了分类。提出了一种将正交调制LFM信号产生系统的幅相误差映射到基带后，在数字域利用复系数FIR滤波器进行校正的方案。针对直接数字波形合成LFM信号产生系统，将误差校正方法简化为直接对存储的数字波形进行预失真处理。最后将校正方法应用于实际系统，结果表明提出的幅相误差校正方案易行、有效，能明显提高输出LFM信号的性能。     

数字阵列MST雷达幅相标校系统设计

数字阵列MST雷达是有源相控阵气象雷达,可探测中层、平流层和对流层的大气风场.该雷达采用了分布式全固态发射技术以及数字波束形成技术,减少了硬件的复杂性,提高了探测性能,更适用于复杂天气过程的探测.幅相标校技术是数字阵列MST雷达的关键技术之一,该技术可以提高雷达的幅相一致性,从而提高雷达的探测性能.文中首先介绍了数字阵列MST雷达的系统组成,然后采用了矩阵分析的方法推导了幅相标校算法,给出了幅相标校系统设计流程,最后得出了一组实际标校结果.     

数字阵列天气雷达系统设计

针对机械扫描天气雷达数据率低,难以对龙卷风等快速变化的中小尺度天气过程进行及时预警的缺点,提出一种用于强风暴探测的数字阵列天气雷达.与传统相控阵雷达相比,数字阵列雷达具有幅相控制精度高、系统瞬时动态范围大、测量精度高等性能优势,该方案采用相位扫描和机械扫描相结合的工作方式以及宽波束发射、多波束同时接收技术,具有高数据率、低成本以及能同时跟踪多个天气单体等性能优势,具有一定的实用价值.     

基于幅相量化的数字射频存储技术

提出了一种新的基于幅相量化的数字射频存储(DRFM)技术,阐述了它的工作原幅相/相幅转换器的设计思路.通过将幅相量化DRFM与传统的幅度量化和相位量化DRFM的性能进行比较,分析其特点与优势.最后使用软件对此系统进行建模仿真.     

基于幅相量化的DRFM技术研究

本文在分析幅相量化DRFM的原理和性能的基础上，结合幅相量化的关键技术特点，采用幅相量化技术设计实现了数字储频系统。     

基于模糊控制的自适应幅相补偿控制系统

针对数字阵列在使用过程中存在的性能退化问题,利用模糊控制相关理论建立了自适应幅相补偿控制器模型,并设计了新型数字阵列自适应幅相补偿控制系统。该控制系统能够智能、实时地对数字阵列进行监测,并根据阵面状态对各通道幅相进行动态调整,实现数字阵列性能的优化。该系统在未来数字相控阵雷达设计中具有很大的工程意义。     

PCM/FM遥测中频数字化接收机设计与实现

本文利用高速高精度数据采集、数字下变频DDC(Digital Downconversion)CORDIC(Coordinate RotationDigital Computer)数字鉴相、一阶差分鉴频和均匀采样二阶数字锁相环DPLL(Digital Phage—Locked Loop)去除多谱勒频率和载波频偏等技术完成了2MHz码速率10.7MHz中频频率的PCM/FM遥测中频数字化接收机设计,并给出了实现系统接收线性动态范围和不同输入信噪比条件输出信号波形的测试结果。测试结果表明,设计系统的接收线性动态范围可达50dB以上,而在输入信噪比≤7dB的情况下设计系统还可以正常工作。     

A UHF mobile telephone system using digital modulation: Preliminary study

A UHF mobile telephone system using digital modulation is described. The system uses on-off keying of an 836-MHz carrier, the code being supplied by an adaptive delta coder with a clock frequency of 50 kHz. The maximum audio baseband signal-to-noise ratio is approximately 30 dB. The mobile receiver employs space diversity in a maximal-ratio combiner. Due to the use of amplitude modulation of the carrier rather than exponential modulation, the diversity receiver is very simple. The system was tested in the laboratory and in the field. Field tests were made in suburban and urban areas. For the four-branch system, threshold occurred at an average IF signal-to-noise ratio of approximately 12 dB.     

Design and Performance of a Digital Multifrequency Receiver

An experimental multifrequency receiver for recognition of digitally encoded multifrequency signaling was designed, constructed and tested. The receiver is based on a quadrature detection technique that consists of digital demodulation followed by second-order, lowpass digital filtering. The post filtering processing produces an estimate of the amplitude of each of the six multifrequency tones and provides suitable information for thresholding and timing measurements. The receiver performs correctly even when subjected to severe environmental conditions including an analog signal range of 23 dB, 10 ms signal interruptions ('hits') and 20 ms signal spacings. The receiver's operation demonstrates the robustness of the digital signal processing techniques employed. The design of the receiver exploits the use of subsampling techniques to increase the efficiency of the hardware through greater multiplexing. When using subsampling, 128 multifrequency receivers with 16-bit words are realized with 6.5 dual-in-line packages per receiver; commercial TTL logic circuits, a 4-bit serial-parallel pipeline multiplier circuit, serial data and a 16.384 MHz clock are assumed.     

Performance of the cross-correlator receiver for binary digitalfrequency modulation

The error probability of the cross-correlator receiver for binary digital frequency modulation (FM) detection is studied using theoretical analysis and computer simulations. The index of performance is taken as the bit-error rate (BER). The BER results obtained permit the selection of an optimum combination of modulation index and receiver bandwidth. This selection is carried out and is compared for analysis based on both computer simulation and theoretical calculation. The performance of the cross-correlator is also compared to that of the limiter-discriminator, and is found to be similar. This is noteworthy because the general I/Q demodulator structure of the cross-correlator is ideally suited to DSP chip implementation, and furthermore, severe amplitude limiting does not have to be performed on the input signal to the receiver. Input signal amplitude variations of up to 20% of the average signal value can be tolerated with only a 1-dB loss in performance, and the receiver is completely independent of the rate of amplitude variation. The theoretical analysis of the receiver uses a Fourier series approach which takes into account the effects of FM distortion and intersymbol interference (ISI). Theoretical and simulation results are found to agree within 0.5 dB in E_b/N_o. We also address the issue of timing recovery. Results obtained indicate that losses due to timing error can be reduced to less than 0.5 dB in E_b/N_o      

应用于数字广播的镜像抑制混频器的设计

在二次变频低中频结构的DRM／DAB数字广播射频极宽频带（148．5kH～1492MHz）接收机中,为了实现良好的镜像抑制性能,第二次变频采用双正交混频器结构。与单正交结构相比较,双正交型混频器具有更优的镜像抑制性能以及更高的成品率。考虑到宽带以及系统输出信号的信噪比,本文中采用了结合多级多相滤波器的双正交下变频有源混频器,在满足镜像抑制要求的的同时提供一定的增益。经理论分析和实际仿真结果表明,该结构的混频器具有良好的镜像抑制性能,镜像抑制比在DRM模式下IIR〉48dB,DAB模式下IIR〉55dB,而且对正交信号幅度和相位的失配不敏感,能够满足数字广播接收机射频前端的所需指标要求。目前整个芯片正在测试中,最终芯片将在Himalaya公司的接收机上进行整机验证。     

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5$^{circ}$ and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.      

中频快速DAGC算法及其FPGA实现

针对中频接收机大动态范围与高灵敏度的要求,提出了一种中频快速数字自动增益控制(DAGC)算法。该算法通过对正交视频信号进行符号判别实现快速幅度检波和门限比较,利用多级双门限分段线性化的方法实现数字对数放大(DLA),结合使用数控衰减器(DCA)扩大中频接收机的输入动态范围。给出了基于FPGA的中频快速DAGC实现方案。实际应用证明,采用该方案的数字化中频接收机在保证接收灵敏度为-58 dBm的情况下,动态范围可达80 dB以上。     

一种幅相一致性高可靠LC滤波器设计

针对批量生产的相控阵雷达发射-接收(T/R)组件对滤波器的幅相一致性要求较高的问题,该文分析了影响LC滤波器幅相一致性的因素,并从产品的电路原理和结构方面对与产品可靠性有关的元器件、工艺流程等因素进行了分析,设计了一款3 GHz带外抑制大于60 dB、多只间相位一致性≤5°、多只间幅度一致性≤0.2 dB的滤波器。结果表明,该滤波器具有较好的矩形系数、带外抑制和高幅相一致性,产品用于某高可靠星载系统T/R组件中,实现了批量生产对幅相一致性的要求。     

A low-cost multichannel optical transmission system for videosignals

A novel low-cost multichannel optical transmission system for video signals is described. The system uses time-division multiplex pulse-position modulation (TDPPM). The transmitter and receiver are realized in a standard bipolar process while an external low-cost laser and PIN photodiode are used. A maximum of 16 channels can be multiplexed, while achieving a weighted signal-to-noise ratio (SNR) of 54 dB, a differential gain of 1% and a differential phase of 0.5°. For a launched power of 0 dBm (pulse amplitude), the optical budget for a 45 dB weighted SNR exceeds 20 dB. Besides video signals the system is also capable of handling other signals such as digital coded audio signals or computer data. The feasibility of a four-channel system has been confirmed by measurements     

A Low‐Crosstalk Design of 1.25 Gbps Optical Triplexer Module for FTTH Systems

In this paper, we analyzed and measured the electrical crosstalk characteristics of a 1.25 Gbps triplexer module for Ethernet passive optical networks to realize fiber‐to‐the‐home services. Electrical crosstalk characteristic of the 1.25 Gbps optical triplexer module on a resistive silicon substrate should be more serious than on a dielectric substrate. Consequently, using the finite element method, we analyze the electrical crosstalk phenomena and propose a silicon substrate structure with a dummy ground line that is the simplest low‐crosstalk layout configuration in the 1.25 Gbps optical triplexer module. The triplexer module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and an analog photodetector as a cable television signal receiver. According to IEEE 802.3ah and ITU‐T G.983.3, the digital receiver and analog receiver sensitivities have to meet ‐24 dBm at BER=10^?12 and ‐7.7 dBm at 44 dB SNR. The electrical crosstalk levels have to maintain less than ‐86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the dummy line with 100 μm space from the signal lines and 4 mm separations among the devices satisfies the electrical crosstalk level compared to a simple structure. This proposed structure can be easily implemented with design convenience and greatly reduce the silicon substrate size by about 50 %.     

A single-chip tuner for DVB-T

A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.