非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

开关电流电路主要误差的改善

开关电流电路是一种新型的数据采样技术.针对开关电流电路中的时钟馈通误差与传输误差进行详细分析,构造出一种调整型共源共栅结构的S2I开关电流存储单元,并用HSpice进行仿真,与基本的开关电流存储单元的性能和Matlab中的理想波形进行对比.结果表明该电路性能大大提高,精确完成了对输入波形的采样一保持.     

开关电流电路及其误差分析

开关电流(SI)技术是有望取代开关电容技术的一种新的采样数据技术。首先介绍了开关电流技术的概念及优点,然后以SI电路基本存储单元为例分析了开关电流电路中可能存在的误差。最后,针对电路中存在的失配误差、传输误差、噪声误差及电荷注入误差等提出了一些解决方法,如S2I技术等。     

低误差开关电流存储单元

详细分析了限制开关电流(SI)精度的主要误差,在共源-共栅组态存储单元的基础上,根据在开关晶体管关断前消除反型层可以改善电荷注入误差的原理,提出一种新型低误差开关电流存储单元.其主要思想是通过消除开关晶体管沟道内的可动电荷、降低存储单元的输出电导,以改善电荷注入误差和电导比误差.采用TSMC 0.25μtm CMOS模型参数进行HSPICE仿真,结果表明,该结构能够很好地降低电路误差,提高开关电流电路的精度.     

一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了100倍.     

一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了10 0倍.     

基于遗传算法的开关电流存储电路的设计

针对开关电流存储电路存在固有误差和电路器件参数需要大量手工迭代计算等难题,提出基于遗传算法的开关电流存储电路设计方法.其主要思想是以Class AB栅极接地存储电路为基础,对其进行小信号模型分析,借助遗传算法对电路的电荷注入误差和时间响应性能进行多目标优化,获取电路中器件参数的最优Pareto解.采用0.5μm CMOS工艺参数,对电路进行PSPICE仿真测试.结果表明,优化设计的电路具有存储精度高、响应速度快等优点.     

用于模拟电路行为级建模的自动压扩子波方法

提出了一种新的自动压扩方法,适用于基于子波配置方法的模拟电路行为级建模.该压扩方法采用的压扩函数根据模块输入-输出函数的奇异性自动生成,因而这一方法具有通用性,可应用于任意输入-输出函数的电路模块的建模.与已有的建模方法相比,该方法能有效地降低模拟误差并减少使用基函数的个数.     

用于模拟电路行为级建模的自动压扩子波方法

提出了一种新的自动压扩方法,适用于基于子波配置方法的模拟电路行为级建模.该压扩方法采用的压扩函数根据模块输入-输出函数的奇异性自动生成,因而这一方法具有通用性,可应用于任意输入-输出函数的电路模块的建模.与已有的建模方法相比,该方法能有效地降低模拟误差并减少使用基函数的个数.     

开关电流电路基本单元误差分析及其改进

开关电流技术(SI)是一种可取代开关电容技术的数据采样技术.首先介绍了SI技术,然后以SI电路基本单元为例,分析了SI电路存在的各种误差,并针对这些误差提出了解决方法;最后提出了一种新的改进电路.实验结果表明,采用TSMC 0.35μm工艺参数和Hspice仿真电路,所设计的电路误差小,输出波形理想,从而可达到预期的目的.     

Wavelet Neural Network Approach for Testing of Switched-Current Circuits

Combining the time and frequency location and multiple-scale analysis of wavelet transform with the nonlinear mapping and generalizing of neural network, an efficient defect-oriented parametric test method using Wavelet Neural Network (WNN) for switched-current integrated circuits is proposed. Contraposing to the fully compatible digital CMOS technology and current scaling calculation of SI circuits, parameter cohort of switched current elements is used to compute the sensitivity and gain tolerance and is applied for selecting the test models. The selecting of the appropriate wavelet function based on particular switched current fault signal is discussed, and the number of network input and output nodes are determined by the circuit status and dimension of eigenvector which is the energy of wavelet decomposition coefficient. To simplify configuration of the neural network, the sampled data was preprocessed by wavelet transform. Illustrative examples show that the proposed wavelet neural network method for testing of switched current circuits is effective.     

Analog Implementation of Wavelet Transform in Switched-Current Circuits with High Approximation Precision and Minimum Circuit Coefficients

This paper presents a novel procedure for analog implementation of wavelet transform in switched-current (SI) circuits. An improved hybrid PSO–SQP optimization is employed to precisely approximate the impulse response of a filter to the wavelet base function in time domain. The SI first- and second-order section circuits with minimum coefficients are designed based on infinite-impulse-response digital filter technology. Cascode techniques are occupied to reduce the effects of parasitic elements. Based on these SI first- and second-order section circuits, a parallel wavelet circuit structure is presented to synthesize the approximated wavelet base function. By adjusting the switch clock frequency, the wavelets at different scales can be realized. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results demonstrate the feasibility of the proposed procedure for analog wavelet transform in SI circuits.     

An efficient nonlinear circuit simulation technique

This paper proposes a novel method for the analysis and simulation of integrated circuits (ICs) with the potential to greatly shorten the IC design cycle. The circuits are assumed to be subjected to input signals that have widely separated rates of variation, e.g., in communication systems, an RF carrier modulated by a low-frequency information signal. The proposed technique involves two stages. Initially, a particular order result for the circuit response is obtained using a multiresolution collocation scheme involving cubic spline wavelet decomposition. A more accurate solution is then obtained by adding another layer to the wavelet series approximation. However, the novel technique presented here enables the reuse of results acquired in the first stage to obtain the second-stage result. Therefore, vast gains in efficiency are obtained. Furthermore, a nonlinear model-order reduction technique can readily be used in both stages making the calculations even more efficient. Results will highlight the efficacy of the proposed approach     

Realization of wavelet transform using switched-current filters

A method for realizing wavelet transform (WT) is presented, in which the WT is synthesized by a bank of switched-current (SI) filters whose impulse responses are the basic wavelet function and its dilations. SI circuits are well suitable for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the sampling frequency. In this article, the wavelet base is approximated by a systematic algorithm with all the involved approximation parameters taken into account. Also, the SI filter employing the follow-the-leader feedback (FLF) multiple-loop feedback (MLF) structure is proposed to synthesize the approximation function. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results indicate that the proposed method has the merits of high approximation accuracy, strong stability and low sensitivity.     

基于Laplace分布的非下采样小波包脉冲星信号消噪

为了提高脉冲星信号的去噪效果,提出了一种基 于非下采样小波包(NWP)分解的局部Laplace模型消噪方法。 首先对真实脉冲星信号进行NWP分解,统计真实脉冲星信号NWP系数的分布特性, 建立真实脉冲星信号小波包系数的Laplace分布模型;然后在Laplace先验概率分布的基础 上,根据最大后 验概率(MAP)估计准则,利用含噪脉冲星信号的小波包系数对真实脉冲星信号的小波包系数 进行有效估算;最后 对估算出的小波包系数进行NWP重构,得到消噪后的脉冲星信号。采用不同 的脉冲星信号进行实 验分析的结果表明,与经典的基于高斯分布的非下采样小波(NSW)消噪和NWP消噪相比,本文 方法可以 更有效地去除噪声,同时更好地保留信号中的微脉冲等细节信息,在信噪比(SNR)、均方根误差(RMSE)、相关系数(CC)和峰值相对误差(REPV)等都 有较好的改善。     

Analog VLSI implementation of wavelet transform using switched-current circuits

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.     

模拟大规模电路的快速频域小波配置法

提出了一种求解状态方程的方法:频域快速小波配置法.通过将状态方程转入频域求解,并对输出变量直接进行小波展开.这一方法比原有的时域快速小波配置法大大减少了未知变量的数目,从而使计算速度和存储空间都有很大程度的改善.由于小波函数及其反变换均有显式的数学表达式,这一方法在得到频域解析近似解的同时就可以获得时域解析近似解,无须在计算过程中进行耗时的数值积分反变换.同时通过自适应算法的引入,这一方法可以有效提高计算效率.     

Analog wavelet transform using multiple-loop feedback switched-current filters and simulated annealing algorithms

A new approach for implementing continuous wavelet transform (CWT) based on multiple-loop feedback (MLF) switched-current (SI) filters and simulated annealing algorithms (SAA) is presented. First, the approximation function of wavelet bases is performed by employing SAA. This approach allows for the circuit implementation of any other wavelets. Then the wavelet filter whose impulse response is the wavelet approximation function is designed using MLF architectures, which is constructed with SI differentiators and multi-output cascade current source circuits. Finally, the CWT is implemented by controlling the clock frequency of wavelet filter banks. Simulation results of the proposed circuits and the filter banks show the advantages of such new designs.