超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素．数值求解的结果表明：镜像势引起的势垒降低对超薄栅MOS直接隧穿电流有较大的影响．利用WKB近似方法,获得了镜像势对直接隧穿电流影响的定性表达式．镜像势对直接隧穿电流的影响随着栅电压的减小而增大,但是随着栅氧化层厚度的减小而减小．     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属-氧化物-半导体场效应晶体管的氧化层的影响.对于栅厚为3nm的超薄栅MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响,数值模拟的结果表明:界面粗糙度对电子的直接隧穿有较大的影响,且直接隧穿电流随界面的粗糙度增加而增大,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小.     

轴向应变对双势垒结构共振隧穿的影响

首先介绍了共振隧穿理论和一种新效应--介观压阻效应,对AlxGa1-xAs/GaAl/AlxGa1-xAs共振隧穿双势垒结构的轴向施加压应变作了分析,然后计算了轴向应变对垒宽和垒高的影响,对透射系数和隧穿电流用Matlab作了仿真.发现压应变可以使隧穿电流线性增加,偏压不同电流增加的速率也不同,为设计共振隧穿器件提供了理论依据.     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

On the tunneling component of charge pumping current in ultrathingate oxide MOSFETs

A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

Dynamic oxide voltage relaxation spectroscopy

A new method for trap characterization of oxidized silicon is described. The Dynamic Oxide Voltage Relaxation Spectroscopy (DOVRS) is an improved version of the formerly proposed Oxide Voltage Relaxation Spectroscopy (OVRS) technique which applies a periodic long duration constant current for tunneling injection. It has been demonstrated that the new technique can be used not only to separate and identify the oxide trap from interface trap, but also to separate and determine the centroid from the oxide trap density generated in the MOS system by the tunneling current stress. In the pulse constant current mode, the OVRS measurement can be completed instead of using the double current-voltage technique. Thus the new method results in more accurate and quicker measurements of the oxide trap centroid. Analytical expressions for computing the paramaters of the interface and oxide traps are derived. The effect of the channel carrier mobility on the spectroscopy is also considered. Two types of oxide and two types of interface traps were observed at a pulse constant Fowler-Nordheim current stress by the new method of DOVRS     

γ射线辐照对130 nm部分耗尽SOI MOS器件栅氧经时击穿可靠性的影响

研究了射线辐照对130 nm部分耗尽（Partially Depleted,PD）绝缘体上硅（Silicon on Insulator,SOI）工艺MOS器件栅氧经时击穿（Time-Dependent Dielectric Breakdown,TDDB）寿命的影响。通过测试和对比辐照前后NMOS和PMOS器件的转移特性曲线、阈值电压、关态泄漏电流以及TDDB时间等电参数,分析了射线辐照对PD-SOI MOS器件TDDB可靠性的影响。结果表明:由于射线辐照在栅极氧化层中产生了带正电的氧化物陷阱电荷,影响了器件内部势垒的分布,降低了电子跃迁的势垒高度,导致了电子遂穿的正反馈作用增强,从而缩短了器件栅氧化层经时击穿时间,最终造成器件栅极氧化层的可靠性下降。     

The effect of transition region on the direct tunneling current and Fowler–Nordheim tunneling current oscillations in ultrathin MOS structures

The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region.