共查询到19条相似文献,搜索用时 203 毫秒
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SOC中Data-Path布图设计面临的挑战 总被引:7,自引:0,他引:7
目前所设计的系统级芯片(SOC)包含有多个data-path模块,这使得data-path成为整个G大规模集成电路(GSI)设计中最关键的部分.以往的布图理论及算法在许多方面已不能满足data-path布图设计的需要,这主要是由于传统的布图工具没有考虑data-path所特有的电路结构特点.Data-path具有规整的位片结构,具有很高的性能指标要求,如对于时延、耦合效应和串扰等性能都有严格的要求.此外,data-path中还存在大量成束状结构的BUS线网.文中提出了data-path布图设计所面临的挑战.从介绍data-path布图的基本问题入手,重点分析了data-path布图设计中的关键技术,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想. 相似文献
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该文提出一种稳定的面向软模块的固定边框布图规划算法。该算法基于正则波兰表达式(Normalized Polish Expression, NPE)表示,提出一种基于形状曲线相加和插值技术的计算NPE最优布图的方法,并运用模拟退火(Simulation Annealing, SA)算法搜索最优解。为了求得满足固定边框的布图解,提出一种基于删除后插入(Insertion After Delete, IAD)算子的后布图优化方法。对8个GSRC和MCNC电路的实验结果表明,所提出算法在1%空白面积率的边框约束下的布图成功率接近100%,在总线长上较已有文献有较大改进,且在求解速度上较同类基于SA的算法有较大优势。 相似文献
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集成电路布图设计,简称布图设计,在国务院颁布的《集成电路布图设计保护条例》中对其定义为:是指集成电路中至少有一个是有源元件的两个以上元件和部分或者全部互连线路的三维配置,或者为制造集成电路而准备的上述三维配置。相对其他知识产权来说,布图设计专用权还是比较新鲜的事物,大多数人对其还不甚了解。 相似文献
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提出了一种基于CBL布图表示的新的增量式布图规划算法.该算法能很好地解决包括不可二划分结构在内的布图规划问题.针对现有增量式的一些需求,算法给出了相应的高速解决方案.在已有的初始布局的基础上,基于CBL表示方法建立水平约束和垂直约束图,利用图中关键路径和各模块之间的累加的距离松弛量进行增量式操作.对于新模块的插入,在力求面积最小,线长最短和移动模块数目最少的目标指引下能快速地找到最佳位置作为插入点,高效地完成相关操作,算法的时间复杂性仅为O(n).通过对一组来自工业界的设计实例的测试结果表明,该算法在保证芯片的面积、线长等性能不降低甚至有所改善的情况下,运行速度相当快,仅在μs量级,满足了工业界对增量式布图规划算法在速度上的首要要求,同时保证了基本性能的稳定. 相似文献
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An Incremental Algorithm for Non-Slicing Floorplan Based on Corner Block List Representation 总被引:1,自引:0,他引:1
提出了一种基于CBL布图表示的新的增量式布图规划算法.该算法能很好地解决包括不可二划分结构在内的布图规划问题.针对现有增量式的一些需求,算法给出了相应的高速解决方案.在已有的初始布局的基础上,基于CBL表示方法建立水平约束和垂直约束图,利用图中关键路径和各模块之间的累加的距离松弛量进行增量式操作.对于新模块的插入,在力求面积最小,线长最短和移动模块数目最少的目标指引下能快速地找到最佳位置作为插入点,高效地完成相关操作,算法的时间复杂性仅为O(n).通过对一组来自工业界的设计实例的测试结果表明,该算法在保证芯片的面积、线长等性能不降低甚至有所改善的情况下,运行速度相当快,仅在μs量级,满足了工业界对增量式布图规划算法在速度上的首要要求,同时保证了基本性能的稳定. 相似文献
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《信息技术与标准化》1996,(6)
我国将制定半导体集成电路保护条例为了保护我国电子工业中的知识产权,鼓励技术创新,电子部和中国专利局正在抓紧起草《中华人民共和国半导体集成电路布图设计保护条例》。根据条例草案,要取得该条例的保护,必须申请半导体集成电路布图设计登记,提出规定的文件。布图... 相似文献
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静态电流测试是一种高灵敏度、低成本的集成电路失效分析技术,在集成电路故障检测、可靠性测试及筛选中的应用日益普遍。针对某绝缘体上硅专用集成电路在老炼和热冲击实验后出现的静态电流测试失效现象,结合样品伏安特性、光发射显微镜和扫描电子显微镜等电学和物理失效分析手段,确定了栅氧化层中物理缺陷的存在、位置及类型;结合栅氧化层经时介质击穿原理分析,揭示了样品的主要失效机理,并分析了经时介质击穿失效的根源,为改进工艺、提高电路可靠性提供了依据。 相似文献
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《Solid-State Circuits, IEEE Journal of》1987,22(2):233-250
A set of eight chips that perform real-time image-processing tasks was designed and fabricated with a 4-/spl mu/m NMOS technology. The chips include a 3/spl times/3 linear convolver, a 3/spl times/3 sorting filter, a 7/spl times/7 logical convolver, a contour tracer, a feature extractor, a lookup-table ROM, and two postprocessors for the linear convolver. All chips were designed with architectures that are dedicated to the particular image-processing task to be performed. The image-processing circuits operate on 10-MHz video data (512/spl times/512-pixel images). The design time for the chips was kept to 1.5 man-years by reusing hardware and using (and developing) appropriate CAD tools, ROM generators and a data-path generator were developed to reduce the circuit design time. An image recognition system was built with these custom chips that can recognize two-dimensional objects that are characterized by their closed outer contours. The complete system is controlled by a Sun workstation and operates at rates up to 15 frames/s. The recognition system achieved a 98% recognition rate for eight objects over a wide range of orientation and size variations and a 100% recognition rate without size variations. 相似文献
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A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances 总被引:2,自引:0,他引:2
Xuguang Wang Jun Liu Feng Zhu Yamada N. Dim-Lee Kwong 《Electron Devices, IEEE Transactions on》2004,51(11):1798-1804
A simple technique to form high-quality hafnium silicon oxynitride (HfSiON) by rapid thermal processing oxidation of physical vapor deposition hafnium nitride (HfN) thin films on ultrathin silicon oxide (SiO/sub 2/) or silicon oxynitride (SiON) layer is presented. Metal TaN gate electrode is also introduced into such HfSiON stacks. Excellent performances including large electron mobility (85%SiO/sub 2/at0.2 MV/cm), low leakage current (10/sup -4/ of SiO/sub 2/), and superior time-dependant dielectric breakdown reliability are achieved in HfSiON/SiO/sub 2/ stacks, and these results suggest such stacks are very promising for the low-power SOC applications in the near future. In addition, the improvement of the electron mobility in this HfSiON/SiO/sub 2/ stack by a reduction of the border traps in the HfSiON dielectric is demonstrated. 相似文献
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Panner J.H. Abato R.P. Bassett R.W. Carrig K.M. Gillis P.S. Hathaway D.J. Sehr T.W. 《Solid-State Circuits, IEEE Journal of》1991,26(3):300-309
A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8-μm, four-level-metal, single-poly CMOS process, with a 0.45-μm nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip 相似文献
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随着半导体芯片器件规模急剧增长,对芯片的功能验证以及场景验证提出了更多的挑战。而对于基带SOC芯片,挑战则更加显著。基带SOC芯片的设计验证涉及到大量算法、信号处理专用电路、软硬件协同、实时复杂场景等功能评估与验证。一般通用的芯片验证方法(基于测试用例的服务器离线验证以及FPGA原型验证)无法覆盖对基带芯片评估、验证以及测试的要求。针对基带芯片设计验证需求,本文设计并实现了一个基于软件无线电的通用实时原型平台,可满足不同频段、不同协议的基带芯片的算法评估、功能及场景测试需求。本文基于该通用实时原型平台,成功的对一款GPS/BD导航基带芯片进行了实时原型验证,解决了原有离线仿真不能满足的实时场景验证需求,使得基带芯片的验证环境更加贴近真实环境,从而极大的提高了芯片的成功率。 相似文献
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Error-tolerance is an innovative technique to address the problem of low yields in nanometer very large scale integrated (VLSI) circuitry, which is the backbone of the system-on-a-chip (SOC) revolution. The basic principle of error-tolerance is that some chips may occasionally produce erroneous outputs, but still provide acceptable performance when used in certain systems. Using these chips in such systems results in an increase in effective yield. In this paper, a fault-oriented test methodology is presented for classifying whether or not a chip is acceptable based on error rate estimation. A sampling method is proposed to estimate error rate associated with each possible fault in the target circuit. According to this information, an approach is developed to identify a list of faults that are acceptable with respect to a specified upper bound on expected error rates of acceptable chips. Furthermore, a test pattern selection method, and an output masking technique are presented to identify tests which detect all of the unacceptable faults, and as few acceptable faults as possible, so as to maximize the effective yield. Experimental results indicate the high effectiveness of the proposed error rate estimation method, and the degree to which yield can be enhanced. 相似文献
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传统无线网络协议栈存在硬件兼容性弱、内存和CPU占用率高、函数接口复杂等问题,采用此类协议栈将提高项目开发的软硬件成本。设计一种轻量级分层协议栈,通过协议栈架构的分层设计、底层的开放式设计、函数的可重入设计等,使其具有低系统资源占用率、高可移植性和多网卡协同工作的特点。采用IAR EW8051,KEIL MDK,STM32CUBE等作为软件平台,进行协议栈程序的开发与测试。测试结果表明,该协议栈代码量小,可应用于CC1100,CC2500,SI4463, SX1278等无线芯片,且能有效应对复杂环境下的信号干扰,提升点对多通信效果,有较高的实用价值。 相似文献
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根据深亚微米SOC设计的特点和需求,提出了一种新的基于模块的全芯片分层设计方法,它把系统架构、逻辑设计以及物理实现有机结合到一起.通过渐进式时序收敛完成芯片的层次规划,并最终达到一次实现芯片级的时序收敛,大大提高了深亚微米SOC设计的效率,并在实际设计之中得到了有效验证. 相似文献