有源忆阻器伏安关系与有源忆阻电路频率特性研究

忆阻器是具有记忆特性的非线性电阻器,是物理上新实现的第四种基本二端电路元件.以分段二次型非线性函数描述的有源磁控忆阻器为例,分析了有源忆阻器的伏安关系,研究了有源忆阻器与电容串联电路(简称有源WC电路)的频率响应特性,并与有源RC电路进行了比较分析.结果表明:有源忆阻器的伏安特性曲线为紧磁滞回线,且依赖于其内部初始状态;有源WC电路与有源RC电路均呈现高通特性,但前者为超前网络而后者为滞后网络.基于有源磁控忆阻器的等效电路进行了电路仿真,其结果很好地验证了理论分析结果.     

基于忆阻器的低通滤波器设计

忆阻器是一种新型的非线性二端无源器件,具有电阻、电容和电感所不具备的记忆特性.使用忆阻器和由忆阻器构成的忆容等效电路设计了二阶无源低通滤波电路和有源低通滤波电路.SPICE仿真实验结果证实了设计的可行性.所设计的低通滤波电路在电路参数调整和稳定性方面相比于传统的低通滤波电路具有较大的优势.     

基于荷控忆阻器的四阶混沌电路

近年来,基于亿阻器的混沌电路受到国内外学者的广泛关注.然而现阶段的研究,大都采用通过磁控忆阻器和负电导并联构成的有源忆阻器替代蔡氏电路中蔡氏二极管的方法.而采用荷控忆阻器的混沌电路大都同时使用荷控忆阻器与磁控忆阻器构成的五阶双忆阻器混沌电路.该文在蔡氏电路的基础上,采用荷控忆阻器与电感串联的形式构造了一个新的四阶忆阻混沌电路,并提出改进的忆阻器非线性特性曲线,通过数值仿真的方法进行了验证.最后,对这个新的四阶忆阻混沌电路进行动力学特性分析,主要通过李雅普诺夫指数和吸引子在相平面的投影.     

忆阻高通滤波电路准周期与混沌环面簇发振荡及慢通道效应

该文提出了一种忆阻高通滤波电路,它是由有源高通RC滤波器与二极管桥级联LC振荡器的忆阻模拟器并联耦合组成的。该文建立了电路方程与系统模型。基于分岔图、相平面图、庞加莱映射等数值仿真,开展了以反馈增益为可调参数的分岔分析,揭示了忆阻高通滤波电路中存在的准周期、混沌环面、混沌和多周期等簇发振荡行为。进一步地,通过快慢分析法,导出了快子系统的Hopf分岔集,并进而阐述了忆阻高通滤波电路慢通道效应的形成机理。最后,基于Multisim电路仿真验证了数值仿真结果。     

数字控制忆阻型自适应滤波电路设计

忆阻器是除继电阻、电容和电感之外的第4种基本双端电路元件,具有频率滞后性和阻值易控性等特点。该文从理论上推导和数值仿真上验证了HP实验室提出的铂-二氧化钛-铂(Pt-TiO2-Pt)无源忆阻器与初始状态相关的频率特性,并依据其特性设计了一类数字控制忆阻型自适应滤波电路,利用电路改变忆阻器初始状态忆阻值进而改变滤波电路截止频率实现选频。     

数字控制忆阻型自适应滤波电路设计

忆阻器是除继电阻、电容和电感之外的第4种基本双端电路元件,具有频率滞后性和阻值易控性等特点。该文从理论上推导和数值仿真上验证了HP实验室提出的铂-二氧化钛-铂(Pt-TiO2-Pt)无源忆阻器与初始状态相关的频率特性,并依据其特性设计了一类数字控制忆阻型自适应滤波电路,利用电路改变忆阻器初始状态忆阻值进而改变滤波电路截止频率实现选频。     

荷控忆阻器等效电路分析模型及其电路特性分析

荷孔忆阻器是一种具有记忆功能的二端式电路元件,按照Φ-q关系式与泰勒级数模式所构建的荷控忆阻器等效电路分析模型,对三次非线性荷控忆阻器模型进行深入探究分析,面向基于不同参数条件的荷控忆阻器特性开展研究,即是否有源性以及伏安关系等等。经过分析可以得出,忆阻器伏安关系拥有斜体8字形紧磁滞的回线特点,随着参数符号改变,荷控忆阻器同样会于有源性与无源性间实时转换,使得电路特性也随之变化。相比无源性荷控忆阻器,有源性荷控忆阻器更加适用于二次谐波信号。     

基于忆阻元件的五阶混沌电路研究

采用一个有源磁控忆阻器替换四阶蔡氏振荡器中的蔡氏二极管,导出了一个基于忆阻元件的五阶混沌电路,建立了相应电路状态变量的微分方程组.理论分析表明该忆阻混沌电路具有一个平衡点集,其稳定性随忆阻器初始状态变化而变化.采用常规的动力学分析手段研究了忆阻器初始状态发生变化时电路的动力学特性.数值仿真结果验证了理论分析的正确性.     

基于双曲函数的通用型荷控忆阻器电路等效模型分析

目前,忆阻器模拟器的研究主要集中在磁控忆阻器,对荷控忆阻器模拟器的研究不多,双曲函数型的荷控忆阻器模拟器也很少涉及。因此,该文提出一种基于双曲函数的通用型荷控忆阻器模拟器。模拟器通过电压-电流的相互转换电路,实现电路中电压和电流信号之间的相互转换,再通过电路中对应的电路模块对产生的信号进行计算,最终得到通用型双曲荷控忆阻器模型。模拟器能够实现双曲正弦、双曲余弦以及双曲正切函数对应的荷控忆阻器模型。通用型双曲函数荷控忆阻器模拟器对应的等效电路,主要由运算放大器、电阻、电容、三极管等基本元件组成。分析模拟器在不同幅值以及不同频率的输入信号下的伏安特性曲线,得出荷控忆阻器模拟器符合记忆元件的基本特性。该文提出的通用型双曲函数荷控忆阻器模型,对忆阻器模型的发展具有一定的参考意义。     

基于E型频变负阻的五阶椭圆高通滤波器设计

用电流传送器实现的E型频变负阻、接地电感和浮地电感作为单元电路,提出了实现高阶椭圆高通滤波器的设计方法.用该方法设计的有源滤波电路具有无源梯形网络原型的低灵敏度特性,给出了五阶椭圆高通滤波器的设计例子和PSPICE仿真结果.     

并联型忆阻器混沌电路设计

利用磁控忆阻器、电感和电容三个元件并联设计了一种新型忆阻器混沌电路。采用常规的动力学分析方法研究了系统的基本动力学特性,例如相图、平衡点稳定性分析、李雅普诺夫指数谱和分岔图。结果表明该系统产生了一类特殊混沌吸引子,且随系统参数改变,系统可以产生丰富的混沌行为。为验证电路混沌行为,利用Pspice进行了相应的电路仿真,仿真结果与理论分析、数值仿真基本一致。     

On memristor ideality and reciprocity

Starting from the constitutive properties that underpin the ideal memristor as originally defined by Leon Chua, we identify the conditions under which two memristors comply with the reciprocity theorem. In particular, we explore the minimal set of requirements for an ideal memristor and the physical implications of not complying with these criteria. Then, we show that reciprocity is satisfied when two identical ideal memristors with the same initial memristance are connected such that the output of the first one is taken as the input of the second; the output of the second memristor then matches exactly the initial input of the first device. We also discuss under which conditions non-ideal memristors can be reciprocal and how this property may be exploited in applications.     

Emergent spiking in non-ideal memristor networks

Memristors have uses as artificial synapses and perform well in this role in simulations with artificial spiking neurons. Our experiments show that memristor networks natively spike and can exhibit emergent oscillations and bursting spikes. Networks of near-ideal memristors exhibit behaviour similar to a single memristor and combine in circuits like resistors do. Spiking is more likely when filamentary memristors are used or the circuits have a higher degree of compositional complexity (i.e. a larger number of anti-series or anti-parallel interactions). 3-memristor circuits with the same memristor polarity (low compositional complexity) are stabilised and do not show spiking behaviour. 3-memristor circuits with anti-series and/or anti-parallel compositions show richer and more complex dynamics than 2-memristor spiking circuits. We show that the complexity of these dynamics can be quantified by calculating (using partial auto-correlation functions) the minimum order auto-regression function that could fit it. We propose that these oscillations and spikes may have similar phenomena to brainwaves and neural spike trains and suggest that these behaviours can be used to perform neuromorphic computation.     

Floating memristor emulator with subthreshold region

Memristor which is recently discovered and known as missing circuit element is an important for memory, nonlinear and neuromorphic circuit designs. Modeling of memristor devices is essential for memristor based circuit design. In this paper, compact memristor which has high memristance value is introduced. The simulations are completed in LTspice program and expected results are obtained applying sinusoidal. Two memristor emulators are connected in serial, in parallel and promising results presented. The simulation results of applying positive pulse train to both of terminals of memristor are showed. The simulations of the proposed emulator showed the expected memristor characteristics.     

Leon Chua's memristor [Recognitions]

Recounts Leon Chua's discovery of the memristor and the example Chua set for younger generations of scientists and engineers.     

A bridge technique for memristor state programming

ABSTRACT

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is flowing through the device. Using such an approach reading the state and its adjustment are done simultaneously, which reduces the programming latency. In the proposed method, instead of tuning the memristance, the state of the memristor will be set to the desired value, which is proportional to a control voltage. The low programming latency, six-bit accuracy, and use of a simple circuit for programming, are the main advantages of our solution. The proposed circuit is designed and laid out in 0.35 µm CMOS technology and takes 0.0273mm². Furthermore, the proposed approach is applied to a memristor emulator to demonstrate its correct operation in real applications.     

An accurate model of domain-wall-based spintronic memristor

Spintronic memristors are promising devices that can be used in various applications such as memory chips and neuromorphic systems. The spintronic memristor combines the non-volatility advantage of resistive memristors, and the good scalability, and radiation hardness of spin-transfer torque magnetic devices. In addition, spintronic memristors can benefit from the maturity of integrating magnetic devices on top of CMOS devices. Current models of spintronic memristor only provide a similar version of the linear ion drift model of resistive memristors, which offers a simplified model, but with low accuracy and without enough linking to the device's physical parameters. In this paper, an accurate model of domain-wall- based spintronic memristor based on Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation is proposed. The proposed model provides a more accurate dynamical behavior by using the LLGS equation, and better relation to the device's physical parameters. It also uses the required equations that cover different types and geometries of spintronic memristors. The effect of the thermal fluctuations on device's parameters is also included into the model. The model uses the theory of domain-wall motion to explain the behavior of the device. Furthermore, a Verilog-A model is developed in order be compatible with IC CAD tools.     

Design of a memristor based fuzzy processor

This paper presents a mixed-signal hybrid CMOS/Nano circuit to implement a fully programmable fuzzy processor that performs the zero-order Sugeno's algorithm. The programmability is incorporated in both the rule base and the membership function generator. Membership functions are stored in a memristor-based crossbar array, whereas digital memory is utilized to form a rule base. Each linguistic value whose shape can be independently chosen is stored in each row of the crossbar. Moreover, the adjacent linguistic values can have any order of overlapping ratio. Consequently, a very powerful and flexible fuzzifier is designed.The analog signal processing blocks are designed in both current and voltage mode to simplify the circuit complexity while the digital circuitry is utilized to add programmability to the whole processor. A fuzzy logic controller with nine rules, two inputs, and one output was successfully simulated using HSPICE with 350 nm technology. Simulation results confirm the proper operation of the processor that can operate up to 10 MFLIPS (Mega Fuzzy Logic Inference Per Seconds) while consuming 3.49 mW (@vdd 3.3v). Furthermore, simulation results show that an equivalent precision of 6-bits is achieved in the output signal generation. The circuit is laid out and it takes an area of approximately 0.614 mm².