Notch-δ-doped InP Gunn diodes for low-THz band applications

The viability of the indium phosphide (InP) Gunn diode as a source for low-THz band applications is analyzed based on a notch-δ-doped structure using the Monte Carlo modeling. The presence of the δ-doped layer could enhance the current harmonic amplitude (A₀) and the fundamental operating frequency (f₀) of the InP Gunn diode beyond 300 ​GHz as compared with the conventional notch-doped structure for a 600-nm length device. With its superior electron transport properties, the notch-δ-doped InP Gunn diodes outperform the corresponding gallium arsenide (GaAs) diodes with up to 1.35 times higher in f₀ and 2.4 times larger in A₀ under DC biases. An optimized InP notch-δ-doped structure is estimated to be capable of generating 0.32-W radio-frequency (RF) power at 361 ​GHz. The Monte Carlo simulations predict a reduction of 44% in RF power, when the device temperature is increased from 300 ​K to 500 ​K; however, its operating frequency lies at 280 ​GHz which is within the low-THz band. This shows that the notch-δ-doped InP Gunn diode is a highly promising signal source for low-THz sensors, which are in a high demand in the autonomous vehicle industry.     

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

Electrical and structural properties of hafnium silicate thin films

Thin (4 nm) hafnium silicate (HfO₂)_x(SiO₂)_1−x/SiO₂ gate stacks (0 < x < 1) grown by metal organic chemical vapour deposition (MOCVD) are investigated in this study. The focus is on extracting the optical constants, and hence bandgaps as well as dielectric constants. The VUV (vacuum ultraviolet) spectroscopic ellipsometry (VUV-SE) technique in the spectral range 140–1700 nm, together with current–voltage and capacitance–voltage techniques were used for studying the optical and electrical properties of the layers, respectively. The bandgap was found to increase from 5.24 eV for HfO₂ to 6 eV for Hf-silicate with 30% Hf. The permittivity was reduced from 21 for HfO₂ layers to 8 for Hf-silicate with x = 0.3. The results suggest that the optimal Hf content is above 0.6, for which the permittivity higher than 10 can be achieved.     

New dielectric material system of Nd(Mg1/2Ti1/2)O3–CaTiO3 at microwave frequency

The microwave dielectric properties of (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ (0.1  x  1.0) ceramics prepared by the conventional solid state method have been investigated. The system forms a solid solution throughout the entire compositional range. The dielectric constant decreases from 152 to 27 as x varies from 0.1 to 1.0. In the (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ system, the microwave dielectric properties can be effectively controlled by varying the x value. At 1400 °C, 0.1CaTiO₃–0.9Nd(Mg_1/2Ti_1/2)O₃ has a dielectric constant (ε_r) of 42, a Q × f value of 35 000 GHz and a temperature coefficient of resonant frequency (τ_f) of −10 ppm/°C. As the content of Nd(Mg_1/2Ti_1/2)O₃ increases, the highest Q × f value of 43 000 GHz for x = 0.9 is achieved at the sintering temperature 1500 °C.     

An UTRA/FDD Direct-Downconversion Mixer in 0.25 μm CMOS

In this paper the design of a 2 GHz direct-downconversion mixer for a UTRA/FDD receiver is presented. The mixer is implemented using a standard low-cost 0.25 m, single-poly, six-metal CMOS process. An on-chip passive balun is used to generate a balanced RF input signal. In-house optimized device models are used for both active and passive components to achieve a voltage conversion gain of 12.8 dB, an iIP₂ of 25 dBm, an iIP₃ of –3.1 dBm, and a noise figure of 8 dB. The circuit provides I and Q signal path outputs while drawing 6 mA from a 2.5 V supply.     

RF CMOS technology for MMIC

This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using an optimized 0.13 μm CMOS topology, f_T of 86 GHz and f_max of 73 GHz are obtained, in addition to a NF_min of 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtained using copper interconnect, while capacitors with high unit capacitance and quality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and 25 dB at 0.1 and 2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems.     

A 2.4 GHz CMOS Low-IF Receiver Front-End for WLAN Applications

A CMOS low-IF receiver front-end applied for Wireless Local Area Networks (WLANs) is presented in this paper. The receiver front-end comprises a low noise amplifier (LNA), a down-converter, a single-to-fully converter, a polyphase filter, and a summator/subtractor. This low-IF architecture achieves 0.46° phase error and 0.7 dB gain mismatch in I–Q channels while the 2.4 GHz RF signal is down-converted into 100 MHz of IF band. The cascaded noise figure (NF) of LNA and polyphase network is 4.89 dB within the WLANs' requirement. The chip realized in a 0.6 m CMOS technology occupys 2.4 mm × 2.1 mm active area. From a single 3.3 V power supply, it consumes 300 mW power.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Change in d.c. and 1/f noise characteristics of n-submicron MOSFETs due to hot-carrier degradation

Hot-carrier stress and its influence on d.c. and 1/f noise characteristics in submicron n-channel MOSFETs was investigated. From a 0.5 μm CMOS technology we observed a negative shift in the threshold voltage and a decrease in the drain current. The degradation increases the series resistance on the drain side. In most cases, the relative 1/f noise in the drain current also increases. A degraded device is often found to be noisier in its reverse mode than in its normal mode. The novel material is that the normalized 1/f noise analysis in terms of the 1/f noise parameter α is a more sensitive diagnostic tool for hot-carrier degradation in submicron MOSFETs than S_I (

Full-size image

) and some results are qualitatively explained in terms of mobility fluctuations.     

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (V_th) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.     

A 5.4-GHz high-<Emphasis Type="Italic">Q</Emphasis> tunable active-inductor bandpass filter in standard digital CMOS technology

A transistor-only CMOS active-inductor with an all-NMOS signal path is presented. By tuning the varactor-augmented parasitic capacitance at the only internal node the circuit losses from submicron MOSFETs can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties. Transistor-only second-order bandpass filters using the active inductor were built in the TSMC 0.18-μm CMOS process, and high filter Q was obtained by tuning the varactor. The highest center frequency measured was f ₀ = 5.7 GHz for 0.2-μm gate lengths and the maximum repeatably measured Q was 665. Lower Qs can be obtained by reducing the capacitive compensation or by adjusting the circuit biasing. f ₀ and Q are tunable via separate varactors. IIP ₃ and input 1-dB compression point were simulated as 0.523 V_PP and 0.128 V_PP (−1.65 and −13.9 dBm from a 50-Ω source) at 5.7 GHz with Q = 100 and midband gain equal 4.7 dB. For the same conditions, the output noise and noise figure (R _S = 50 kΩ) were simulated to be 0.8 μV/Hz^1/2 and 25.6 dB, respectively. The filter core occupies an area of 26.6 μm × 30 μm and dissipates 4.4 mW at 5.4 GHz from a 1.8-V power supply. As the circuits use only MOSFETs they are fully compatible with standard digital CMOS processes. f ₀ statistics were obtained by measuring 40 chips at identical biasing condition.     

Reliability results of HBTs with an InGaP emitter

Accelerated lifetest results are presented on HBTs with InGaP emitters. An Arrhenius plot indicates the existence of a temperature dependent activation energy, E_a. A low E_a mechanism dominates above T_j 380 °C and a high E_a mechanism dominates at lower temperature. The critical transition temperature between regimes is determined using the method of maximum likelihood. The difference in E_a’s between low and high temperature regimes is statistically significant.A comparison is made between lifetimes determined from at temperature vs. 40 °C data. No significant difference is observed indicating that beta degradation can be monitored at temperature only and cooling to low temperature is not necessary. Other comparisons indicate that junction temperatures up to 367 °C can still provide good estimates of lower temperature behavior.By the method of maximum likelihood, the predicted MTTF at T_j = 125 °C is 7.6 × 10⁹ h with 95% CBs of [6.4 × 10⁸, 8.9 × 10¹⁰]. Given the typical industry standard of 1 × 10⁶ h, the reliability requirements are easily met.It is suggested that the standard of 1 × 10⁶ h does not adequately capture failure time variation and that a better specification is in terms of fails in time (FITs). The 10 year average FIT rate at 125 °C is found to be negligible. Assuming a much higher junction temperature of 210 °C, the average failure rate climbs to 5 FITs with an upper 95% confidence bound of 40 FITs.     

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Distribution of interface states at the emitter–base heterojunctions in heterostructure bipolar transistors (HBTs) is characterized by using current–voltage characteristics using sub-bandgap photonic excitation. Sub-bandgap photonic source with a photon energy E_ph which is less than the energy bandgap E_g (E_g,GaAs = 1.42, E_g,AlGaAs = 1.76 eV) of emitter, base, and collector of HBTs, is employed for exclusive excitation of carriers only from the interface states in the photo-responsive energy range at emitter–base heterointerface. The proposed method is applied to an Al_0.3Ga_0.7As/GaAs HBT (A_E = W_E × L_E = 250 × 100 μm²) with E_ph = 0.943 eV and P_opt = 3 mW. Extracted interface trap density D_it was observed to be D_it,max  4.2 × 10¹² eV⁻¹ cm⁻² at emitter–base heterointerface.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.