用于交会测量的摄像机标定系统设计

介绍了一种简易的摄像机立体标定系统的设计方案,主要应用于多CCD交会测量技术中,可以完成单个摄像机的标定、多个摄像机之间的立体标定和标定精度评估等功能.建立了包含透镜径向畸变和切向畸变的摄像机成像模型,采用两步法求解摄像机参数,最后通过交会测量得到的多个棋盘格的边长与实际边长的误差量来衡量摄像机标定的精度.该系统不要求使用者具有专业的3D几何知识,速度快,成本低,而且可以达到很高的精度.     

Verification Approach of Metropolis Design Framework for Embedded Systems

In this paper, we focus on the verification approach of Metropolis, an integrated design framework for heterogeneous embedded systems. The verification approach is based on the formal properties specified in Linear Temporal Logic (LTL) or Logic of Constraints (LOC). Designs may be refined due to synthesis or be abstracted for verification. An automatic abstraction propagation algorithm is used to simplify the design for specific properties. A user-defined starting point may also be used with automatic propagation. Two main verification techniques are implemented in Metropolis the formal verification utilizing the model checker Spin and the simulation trace checking with automatic generated checkers. Translation algorithms from specification models to verification models, as well as algorithms of generated checkers are discussed. We use several case studies to demonstrate our approach for verification of system level designs at multiple levels of abstraction.     

Design techniques for testable embedded error checkers

Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability     

Requirements-Level Semantics and Model Checking of Object-Oriented Statecharts

In this paper we define a requirements-level execution semantics for object-oriented statecharts and show how properties of a system specified by these statecharts can be model checked using tool support for model checkers. Our execution semantics is requirements-level because it uses the perfect technology assumption, which abstracts from limitations imposed by an implementation. Statecharts describe object life cycles. Our semantics includes synchronous and asynchronous communication between objects and creation and deletion of objects. Our tool support presents a graphical front-end to model checkers, making these tools usable to people who are not specialists in model checking. The model-checking approach presented in this paper is embedded in an informal but precise method for software requirements and design. We discuss some of our experiences with model checking. Correspondence and offprint requests to: Rik Eshuis, Department of Computer Science, University of Twente, PO Box 217, 7500 AE Enschede, The Netherlands. Email: eshuis@cs.utwente.nl     

An educational software package for Thyristor Switched Reactive Power Compensators using Matlab/Simulink

In this paper, an educational software package called TSCOM (Thyristor Switched Reactive Power Compensators) has been developed. The TSCOM software package contains simulation models of Thyristor Switched Capacitor (TSC) and Thyristor Switched Reactor (TSR)-based Static VAr Compensator (SVC) which are two of the shunt Flexible AC Transmission Systems (FACTS) devices. The design and simulations of TSC and TSR-based SVC are proposed using the Matlab/Simulink 7.04® and SimPowerSystems. The TSC and TSR-based SVC devices are demonstrated at two bus, three bus, infinite-bus, single-phase, three-phase, static load, dynamic load and stair-case load conditions. The effects of TSC and TSR-based SVC devices on load voltage are also analyzed. Student feedback indicates that this package is user-friendly and considerably effective for students and researchers to study theory of switched compensators, the reactive power control and voltage regulation. The proposed package will help to design the practical prototypes for students and researchers.     

Designing checkers for programs that run in parallel

Program correctness for parallel programs is an even more problematic issue than for serial programs. We extend the theory of program result checking to parallel programs, and find general techniques for designing such result checkers that work for many basic problems in parallel computation. These result checkers are simple to program and are more efficient than the actual computation of the result. For example, sorting, multiplication, parity, the all-pairs shortest-path problem and majority all have constant depth result checkers, and the result checkers for all but the last problem use a linear number of processors. We show that there are P-complete problems (evaluating straight-line programs, linear programming) that have very fast, even constant depth, result checkers.This research was done while at the Computer Science Division, University of California, Berkeley, and the International Computer Science Institute, Berkeley, California. Supported in part by an IBM Graduate Fellowship and NSF Grant No. CCR 88-13632.     

Developer-friendly verification of process-based systems

System quality is a key issue in modern systems development. Tool support is essential for checking the system quality efficiently. This is particularly true with respect to the dynamic interactions of the processes within a system. A first generation of checkers – model checkers – provide a basic technology for the verification of process-based systems.Conventional model checkers bear two drawbacks concerning mainly their user-friendliness which impede their broad application. First, model checkers in general do not support the graphical representation of rules (specifications). Although a model may be described with a graphical notation, the specification which has to be checked against the model is generally still text-based. This makes the usage of the checker difficult for process modeling experts. Second, the expressiveness concerning the verification model semantics to be checked is limited to states which are connected by transitions. However, many system development models (e.g. the business process model we use as example) embrace more element types. These are unsupported by the conventional model checkers resulting in a loss of verification precision.The checking system we present in this paper integrates both novelties: the graphical notation for a user-friendly specification and an extended specification language together with a corresponding verifier which supports the checking of many different types of elements (although the paper presents the approach with only two types). The integration is realized by an XML-based transformation system which links the graphical editor to the checking tool.     

New Object-Oriented PROGRES for Specifying the Conceptual Design Tool GraCAD

This paper deals with the application of graph transformations for the specification of conceptual design tools. We show how the graph rewriting system PROGRES is used for specifying the graph part of the conceptual method for architects in which functional requirements of the building to be designed are elicited by means of graph structures. The consistency of the specified requirements and whether a design matches those requirements is verified with graph constraint checkers. We consider how the new object-oriented extensions of the PROGRES language, i.e. packages and node objects with redefinable methods can be used to achieve the required constraint monitoring and preserving functions in the form of graph checker objects. The prototype for our method, called GraCAD, is created with UPGRADE - the recently developed Java framework for developing visual applications based on a PROGRES specification, and the commercial system for architects ArchiCAD.     

Issues in using model checkers for test case generation

The use of model checkers for automated software testing has received some attention in the literature: It is convenient because it allows fully automated generation of test suites for many different test objectives. On the other hand, model checkers were not originally meant to be used this way but for formal verification, so using model checkers for testing is sometimes perceived as a “hack”. Indeed, several drawbacks result from the use of model checkers for test case generation. If model checkers were designed or adapted to take into account the needs that result from the application to software testing, this could lead to significant improvements with regard to test suite quality and performance. In this paper we identify the drawbacks of current model checkers when used for testing. We illustrate techniques to overcome these problems, and show how they could be integrated into the model checking process. In essence, the described techniques can be seen as a general road map to turn model checkers into general purpose testing tools.     

Testing with model checkers: a survey

About a decade after the initial proposal to use model checkers for the generation of test cases we take a look at the results in this field of research. Model checkers are formal verification tools, capable of providing counterexamples to violated properties. Normally, these counterexamples are meant to guide an analyst when searching for the root cause of a property violation. They are, however, also very useful as test cases. Many different approaches have been presented, many problems have been solved, yet many issues remain. This survey paper reviews the state of the art in testing with model checkers. Copyright © 2008 John Wiley & Sons, Ltd.     

Evolutionary-based heuristic generators for checkers and give-away checkers

Abstract: Two methods of genetic evolution of linear and non-linear heuristic evaluation functions for the game of checkers and give-away checkers are presented in the paper. The first method is based on the simplistic assumption that a relation 'close' to partial order can be defined over the set of evaluation functions. Hence an explicit fitness function is not necessary in this case and direct comparison between heuristics (a tournament) can be used instead. In the other approach a heuristic is developed step-by-step based on the set of training games. First, the end-game positions are considered and then the method gradually moves 'backwards' in the game tree up to the starting position and at each step the best fitted specimen from the previous step (previous game tree depth) is used as the heuristic evaluation function in the alpha-beta search for the current step. Experimental results confirm that both approaches lead to quite strong heuristics and give hope that a more sophisticated and more problem-oriented evolutionary process might ultimately provide heuristics of quality comparable to those of commercial programs.     

Parallel search for LTL violations

Recent advances in parallel model checking for liveness properties achieve significant capacity increases over sequential model checkers. However, the capacity of parallel model checkers is in turn limited by available aggregate memory and network bandwidth. We propose a new parallel algorithm that sacrifices complete coverage for increased capacity to find errors. The algorithm, called BEE (for bee-based error exploration), uses coordinated depth-bounded random walks to reduce memory and bandwidth demands. A unique advantage of BEE is that it is well suited for use on clusters of nondedicated workstations.     

对数空间可构造的无向图遍历序列

研究了为无向连通子图设计环状遍历序列（TSC）的空间复杂性问题。通过定义对数空间的Cook归约,分析了TSC问题与无向图连接性问题及通用遍历序列构造问题的关系,证明了TSC问题以及无向图遍历问题是对数空间可解的,并给出了一个TSC一般性构造方法。最后还提出了一个更有效的针对树状图的TSC构造算法。     

Extending model checkers for hybrid system verification: the case study of SPIN

A hybrid system is a system that evolves following a continuous dynamic, which may instantaneously change when certain internal or external events occur. Because of this combination of discrete and continuous dynamics, the behaviour of a hybrid system is, in general, difficult to model and analyse. Model checking techniques have been proven to be an excellent approach to analyse critical properties of complex systems. This paper presents a new methodology to extend explicit model checkers for hybrid systems analysis. The explicit model checker is integrated, in a non‐intrusive way, with some external structures and existing abstraction libraries, which store and manipulate the abstraction of the continuous behaviour irrespective of the underlying model checker. The methodology is applied to SPIN using Parma Polyhedra Library. In addition, the authors are currently working on the extension of other model checkers. Copyright © 2013 John Wiley & Sons, Ltd.     

中压动态无功补偿装置保护系统应用研究

对中压动态(晶闸管投切电容器)无功补偿装置的保护系统进行了研究,较详细地分析了可能发生的故障原因、现象,进行了理论计算,提出了保护措施,为保护系统的设计提供了一定的依据。产品的应用证明,该保护系统较全面地考虑了各种故障保护,简单、实用、可靠,其性能达到设计及工程要求。     

Comparison of checking behavior in adults with or without checking symptom of obsessive-compulsive disorder using a novel computer-based measure

Easy to administer behavioral measures of checking are needed to improve the assessment of this hallmark feature of OCD. We recently developed a new computer-based behavioral assessment of OCD in a previous study. As a follow-up experiment for this method, the goal of this study was to examine whether the new computer-based behavioral assessment would be capable of differentiating behaviors in adults with OCD characterized by checking behavior from those without checking behavior. We compared 22 OCD patients with compulsive checking behaviors (OCD checkers), 17 OCD controls without checking behavior (OCD controls), and 31 healthy controls (HCs) on a novel computer-based behavioral measure of checking behavior. Despite similar levels of successfully completed tasks, OCD checkers demonstrated longer duration of checking behaviors than OCD controls or HCs. Interestingly, no differences were found between OCD controls and HCs in any of the dependent variables. Our new behavioral measure offers a novel, objective, and ecologically valid measure of checking behaviors in a sample of adults with OCD.     

Fault tolerance and digital systems

The paper surveys recent techniques for incorporating selftest and fault-tolerant features into digital systems and comments on their applicability to designs containing VLSI components, such as microprocessors and microcomputers. In particular, the paper covers coding techniques and the design of totally self-checking code checkers; the design of fault-tolerant computer subsystems such as clock generators and semiconductor memory; and techniques for including built-in test facilities and the development of self-test checkout routines. In conclusion, it is suggested that the next major area for research must be the design of fault-tolerant software.     

Safety property verification using sequential SAT and bounded model checking

Model checkers verify properties of safety- or business-critical systems. The main idea behind model checking is to convert a design's verification into a problem of checking key design properties expressed as a set of temporal logic formulas. The graph representing the design's state space then becomes the basis for testing these formulas' satisfiability (SAT). This divide-and-conquer approach provides an overall test for design correctness. We describe a method for checking safety properties using sequential SAT. SSAT can efficiently prove true properties by harnessing the power of bounded model checking (BMC) using SAT, but without the need for a pre-computed correctness threshold. Using a standard set of benchmarks, we conducted experiments to compare the runtime behavior of SSAT with BMC and binary decision diagrams (BDDs).