Low-Voltage Low-Power CMOS RF Four-Quadrant Multiplier

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit was simulated in standard 0.5 μm CMOS level 3 MOSIS (BSIM3 SPICE-based). The mixer has a third-order inter modulation (IM3) of 34.7 dBmV, a third-order intercept point (IP3) of -5.7 dBm, 1-dB compression (P-1dB) of -10.4 dBm and the power consumption is 1.18 mW from a single 1.5 V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption.     

Quantum-inspired evolutionary algorithm for analog test point selection

An important problem that arises in fault diagnosis of analog circuit for fault dictionary technique is the test point selection, which is known to be NP-hard. This paper develops a mathematical optimization model for analog test point selection (ATPS) problem and proposes a novel method to solve it based on quantum-inspired evolutionary algorithm (QEA). The proposed method uses the solution produced by the inclusive algorithm to initialize Q-bit individuals and presents a new fitness function to search the global minimum test point set. In addition, an approach for dynamically determining the magnitude of rotation angle is introduced to accelerate the convergent speed. The efficiency of the proposed algorithm is proven by one practical analog circuit example and a group of statistical experiments. Results show that the proposed algorithm, compared with other methods, finds the global minimum set of test points more efficiently and more accurately.     

Novel Transimpedance Type First-Order All-Pass Filter Using Single Otra

A novel transimpedance-mode first-order all-pass filter configuration is proposed. It uses a single operational transresistance amplifier (OTRA) and few passive components. The proposed circuit is structurally all-pass that does not impose any component matching condition. The proposed circuit is insensitive to parasitic input capacitances and input resistances due to the internally grounded input terminals of the OTRA. It provides an alternative realization of phase equalizers for analog signal processing applications by providing also current-to-voltage conversion. The theoretical results are verified with PSPICE simulations using a CMOS realization of OTRA.     

Analog Circuit Test Point Selection Incorporating Discretization-Based Fuzzification and Extended Fault Dictionary to Handle Component Tolerances

Analog circuit test point selection aims to find the least number of test points that can isolate all the fault modes (including the fault-free case). The fault dictionary, which uses the integer-valued codes to represent the diagnosability of a specific test point, is very popular and saves computation efforts. However, the classical fault dictionary has a limited ability to handle the component tolerances and continuous-valued monitoring variables. To solve the problem, the approach of clustering-based discretization (CBD) is used to abstract the information of data samples distribution. We also develop a new fault dictionary construction technique called extended fault dictionary (EFD). An element of EFD is a set containing either a single integer code or multiple integer codes. The fault isolation rules are redefined, and a novel entropy measure is created in line with CBD of the continuous values. The practical test point selection procedures are presented, which avoids the likelihood to include a redundant test point. Finally, two application studies of circuit test point election are presented, showing that the proposed method provides an effective implementation option for the engineering practice of circuit diagnosis.     

On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis

A method is proposed to obtain a minimal set of test nodes of an analog circuit for isolating all faulty conditions in the fault dictionary approach. Relevant theorem along with the proof is also given. Proposed method is extremely fast. This method is illustrated with an active filter circuit example.     

A New Algorithm for Optimum Multiuser Detection in Synchronous CDMA Systems

Optimum multiuser detection for Code Division Multiple Access (CDMA) systems requires the solution of an NP-hard combinatorial optimization problem. It is well known that the computational complexity of the optimum multiuser detector is exponential with the number of active users in the system. In order to reduce the complexity of the optimum multiuser detection, we propose a Reduced Complexity Maximum Likelihood (RCML) algorithm that includes a set of novel certain boundary rules and characteristics. We investigate the performance and complexity tradeoffs for the RCML algorithm by conducting a set of simulations; Maximum Likelihood (ML) detection as a reference for performance comparisons, and relaxation based Semidefinite Programming (SDPB) algorithm as a reference for complexity comparisons. We show that the RCML algorithm is a promising algorithm for its computational savings over relaxation based algorithms in lightly-to-moderately loaded CDMA systems, and for its optimality in highly loaded CDMA systems.     

Novel All-Pass Filter Section Using Differential Difference Amplifier

A novel high-performance first-order all-pass filter employing a single active element and a minimum number of passive components is presented. The proposed circuit is based on differential difference amplifier and is very suitable for low voltage operation. Also, the use of grounded capacitor enables its implementation with standard CMOS technologies. SPICE simulation and experimental results verifying theoretical analyses are also provided.     

Space-Time Code Construction Using the Code Factorization Technique

A space-time block code construction is presented which achieves maximum diversity for multi-antenna transmission. The construction is based on selected cyclotomic cosets of an extension field which are multiplied together to give a set of transformation polynomials. A space-time factorization code [1] can be constructed by encoding the information vector by different polynomials to form a set of codeword matrices. Codes are constructed over the Galios field GF(2) and mapped to the BPSK signal constellation. The effect of this mapping on the code design criteria is investigated. Simulation results are compared with the statistical properties of the codes based on the design criteria from [2] and [3].     

A Novel Test Point Selection Method for Analog Fault Dictionary Techniques

Most of the recently reported test point selection algorithms for analog fault dictionary techniques are based on integer-coded table (ICT) technique. Hence, the accuracy of these algorithms is closely related to the accuracy of the ICT technique. Unfortunately, this technique is not accurate, especially when the size of fault dictionary is large. This paper proposes an accurate fault-pair Boolean table technique for the test point selection problem. First, the approach to transform the fault dictionary into a fault-pair Boolean table is introduced. Then, a test point selection algorithm based on the fault-pair Boolean table is proposed. Thirdly, several example circuits are used to illustrate the proposed algorithm. Simulated results indicate that the proposed method is more accurate than the other methods. Therefore, it is a good solution for minimizing the size of the test point set.     

Low Voltage Digitally Controlled CMOS Current Conveyor

In this paper, a digitally controlled current conveyo(DCCC) is presented. The proposed DCCC is based on rail-to-rail folded cascode implementation with a current division network (CDN). The CDN is used to provide control on the current gain of the DCCC. The CDN uses a novel current division technique based on differential pairs. The proposed DCCC can operate from ±1.5 V supply voltages. Applications of the proposed DCCC such as variable gain amplifiers (VGA) and digitally tunedfilters have been investigated. PSpice simulations based on the AMI 1.2 µm N-well level 3 parameters are in agreement with the presented work.     

Simplified Design Approach of Reliable Transparent Optical Networks

Transparent optical networks will play an important role in the near future. The aim of this work is to provide a simplified design approach how to utilize the new feature “optical transparency” in WDM based optical networks. Therefore optical nodes and transmission links are characterized and a set of simplified parameters and rules describing the transparent sub-networks is presented. In this way the complexity originating from physical constraints is reduced substantially, simplifying the management of these optical networks and the physical parameters which will be implemented in the routing protocols. This contribution is a compendium of results of the BMBF KomNet project in the field of optical networks optimisation.     

A New and Exact Analysis of DS-CDMA Cellular Radio System Based on the Physical Interpretation of Nakagami Wideband Channel

In this paper we present the performance of two uplink/downlink DS-CDMA receivers in a Nakagami wideband channel. Two detection methods were considered; namely, coherent and differential detection RAKE receivers based on maximal ratio combining technique. We consider a new physical interpretation of the Nakagami channel and the instantaneous power of the multiple access interferers. In comparison with the previous researches in the literature, which are based on Gaussian approximation, this approach results in a more accurate solution for the problem. We analyzed and derived closed form formulae for probability of bit error for DS-CDMA cellular radio system in the Nakagami wideband channel. We presented a set of numerical results for coherent downlink receivers.     

Realization of Voltage and Current Mode KHN Biquads Using CCCIIs

In this work, new Kerwin-Huelsman-Newcomb (KHN) biquads employing current-controlled current conveyors (CCCIIs) in voltage-mode (VM) as well as in current-mode (CM) are presented. The parameters of the proposed circuits can be electronically controlled thanks to the tunability properties of the CCCIIs. The VM circuit is derived from a previously reported one by modifying its summing circuit and replacing the current conveyor(CCIIs) and resistors at their x-input terminals with CCCIIs. On the other hand, the CM circuit is derived from the adjoint graph of the signal-flow graph corresponding to the classical KHN circuit. This circuit is a multi-input single-output CM universal filter, which offers all the main advantages of the CM circuits as well as those of the classical KHN circuit. In addition to the three basic filter responses, they also allow the realization of the notch and the all pass responses.     

Neural Computation of the MoM Matrix Elements for Planar Configurations

In this paper a new artificial neural network (ANN) based model for the calculation of the method of moments (MoM) matrix elements is presented. Training sets that characterize the matrix elements are first constructed. These sets are then utilized to effectively train two radial basis function (RBF) neural networks to accurately estimate all the elements of the MoM matrix for any mesh used. The potential of the proposed approach is demonstrated in the case of a narrow microstrip line. The current distribution on the microstrip line produced by the trained RBF networks agrees very well with the exact distribution. In addition, the proposed ANN model is much faster than the conventional MoM procedure.     

A New Optimal Test Node Selection Method for Analog Circuit

The existing test node selection methods of analog dictionary technique assume that the voltage gap of ambiguity group is 0.7?V. However, this technique is not always accurate to determine the right ambiguity gap for each fault mode. As the probability density of the circuit output approximately satisfies the normal distribution, an accurate technique is introduced to determine the ambiguity gap. Then, this paper proposes a new test node selection method with an extended fault dictionary and the overlapped area values. Firstly, the fault dictionary is constructed with the mean and standard variance values of node voltage. Then, the area detection table is generated by the overlapped area values under normal curves for ambiguity faults, which represent the failure probability of ambiguity faults. Finally, the optimal test node set is selected by fusing fault isolation and overlapped area information. The results show that the proposed method is effective to select the optimal test node set and improve the performance of analog fault diagnosis.     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Fast algorithms for selection of test nodes of an analog circuit using a generalized fault dictionary approach

Selection of test nodes is an important phase of the fault dictionary approach. It is demonstrated in this paper that the techniques used for this purpose in other approaches of analog fault diagnosis like fault analysis and fault verification are not in general suitable for the fault dictionary approach. The ambiguity set is a simple and effective concept for choosing test nodes in the context of dictionaries. These sets are formed such that each faulty condition lies in only one ambiguity set. Deviating from this thinking, overlapping ambiguity sets are proposed in this paper, giving rise to a generalized fault dictionary. These sets use information more fully and hence reduce the number of test nodes. The concept of hashing is applied in this paper for selecting test nodes. This gives a linear time algorithm (linear in the number of fault voltage specificationsf) and it isf times faster than the existing methods. It is not possible to select test nodes faster than this. This technique can also be used to select test nodes by the process of elimination of nodes. This is also linear inf per node elimination. Even a group of nodes can be eliminated or selected within the same computation. This freedom is not possible with the existing methods.     

Electromagnetic Scattering by an Inhomogeneous Impedance Cylinder

In this paper, the electromagnetic scattering problem related to a circular cylinder with inhomogeneous impedance boundary is solved. This kind of problem may have practical applications such as antenna design since one can obtain a certain radiation pattern by choosing thesurface impedance in an appropriate way. The approach presented in this paper is based on the series representations of the scattering and incident fields. The impedance function is also expanded into a Fourier series. By using orthogonality properties of some special functions the problem is reduced to the solution of a system of linear equations. The problem isalso solved through the extended boundary condition method (T-matrix method). Since an extensive treatment of the T-matrix method is available in the open literature the paper is weighted towards the Fourier series method. The results of both methods are compared. Some illustrative examples showing the effects of different parameters on the scattered field are given.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.