多通道NAND闪存控制器的硬件实现

本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。     

Intel超强性能企业级固态硬盘X25-E出货

Intel公司2008年9月初正式发布了自己的SSD固态硬盘产品线,当时针对消费市场的XJ8-M和X25-M已经开始发售。10月15日Intel则宣布,针对企业市场的更高性能型号X25-E已经开始出货。X25-E为2．5寸规格,采用50nm212艺SLCNAND闪存颗粒,通过采用10通道NAND读写架构、NCQ等技术,读取速度达到250MB／s,写人速度为170MB／s。在企业用户更为关心的I／O性能方面,X25-E在4kB随机读取可达到35000 IOPS,4kB随即写入达到3300IOPS,读取延迟75ms,平均无故障工作时间200万小时。     

基于ARM9内核Processor对外部NAND FLASH的控制实现

目前流行的ARM9 CPU中,没有集成NAND FLASH的控制器,可以通过使用NOR FLASH的控制器或者VLIO的控制器,实现对外部NAND FLASH的控制。实测结果显示,用8bI/O的NAND FLASH,在文件系统下读/写的速度为3MB/s,擦除的速度为65MB/s,满足现在流行手持设备对Memory的要求。     

每月新品

MCU/DSP MB91F467D：MCU富士通微电子推出专为下一代汽车应用而设计的闪存MCU-MB91F467D(0．18μm)。该款带1MB嵌入式闪存的32位MCU具有1088KB存储空间。闪存和I-bus、F-bus均可相连,片上预取和灵活的高速缓冲确保了存储器的最佳性能。64KB的嵌入式RAM和外置的总线接口(32位数据,26位地址)可以用来连接外部存储器。三个CAN接口分别独立拥有32个消息缓冲器,五个LIN-UART中四个带有16Byte Rx和TxFlFOs,以加快通信速度。该器件具备8个自由运行定时器,8通道ICU和4通道OCU模块的时基,还有8个重装定时器、3个上升/下降计数器和一个RTC模块,所有定时器可在4MHz主晶振频下或32 kHz子时钟晶振频率下工作。     

宇瞻4GB指纹认证USB闪存

这是宇瞻发布的一款4GB指纹认证USB闪存。与普通闪存储存器不同的是这款USB闪存采用了先进的指纹识别技术,强化了用户的数据安全,是专业人士的最佳选择,同时它也能分割成私人及公共数据空间。它的外部采用耐用的橡胶涂层的金属外壳,不仅时尚美丽．同时也能有效防止表面的刮伤磨损,非常实用。另外它采用USB2．0接口,读取速度最高可达每秒15MB,并支持Windows XP／2000／Vista操作系统。     

闪存风暴 极端享受 SanDisk ExtremeⅢ系列闪存

SanDisk 新近推出的ExtremeⅢ系列闪存包括SanDisk ExtremeⅢ CompactFlash、SD和Memory Stick PRO三种闪存卡。CompactFlash及SD卡的最低读写速度为20MB/s,而Memory Stick PRO的最低读写速度为18MB/s。容量高达1GB～4GB的Extreme Ⅲ系列闪存完全兼容Extreme系列闪存所支持的数码设备,包括时下主流的单镜头反光照相机。Extreme Ⅲ系列闪存采用了SanDisk最新研发的强化并行处理技术(Enhanced Super-Parallel Processing),简称ESP技术。ESP技术结合了他们内部设计的NAND闪存芯片,以及32位RISC处理和先进的运算指令控制…     

基于PXIE总线的高速CCD数字图像采集系统设计

为实现高速电容耦合器件（CCD）数字图像采集传榆,提出一种基于PXIE总线和CameraLink协议的高速图像采集系统设计方案。设计了CameraLink硬件接口电路,实现了视频数据信号的接口设计、控制信号的接12设计、串行通信信号接口设计;同时采用Xilinx公司的Virtex-5LX50T型FPGA作为PXIE传输控制器,并对IP核进行了开发,减少了外围电路设计难度。创新性地运用直接内存访问的工作方式对PXIE传输速度进行优化。实验结果表明,PXIE配置为8通道时,读取数据速率达到1504MB／s,写入速率达到了1490MB／s,可以满足高速CCD数据的传输要求。     

SSD控制芯片提升效能、稳定度与延长使用寿命

慧荣科技宣布推出三款支持MLCFlash SSD（Solid State Drive）的控制芯片,分别是SM2231（PATA接口,支持双信道,读写速度为50MB／s和45MB／s）、SM2233（PATA接口,支持四信道,读写速度为100MB／s和80MB／s）及SM2240（SATA接口,支持四通道,读写速度为110MB／s和80MB／s）。     

SanDisk 8GB MS PRO-HG Duo记忆棒 更大更快更稳定

使用Duo记忆棒的用户终于不再为容量发愁了。全球最大闪存卡生产商SanDisk在6月推出容量40B和8GB的高速大容量MS PRO-HG Duo记忆棒。这两款记忆棒属于SanDisk的高端ExtremeⅢ系列,在读写速度上也有了更大的提高,传输速率可以高达30MB／s。能满足DSLR、PSP、闪存高清摄像机等设备对大容量记忆棒的需求。     

Sandisk Ducati版闪存产品

作为MOTO GP知名大车队意大利的Ducati的赞助商之一，Sandisk推出Ducati版的闪存产品自然是在情理之中。既然与风驰电掣的摩托车品牌挂勾，那么相应的闪存产品自然也应该用速度表态。Ducati版CF卡有4GB与8GB两种容量，传输速率达到了惊人的50MB／s，价格分别为165美元（约合人民币1240元）和315美元（约合人民币2360元）：[第一段]     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²