Investigation of relation between intermetallic and tin whisker growths under ambient condition

The relation between the whisker growth and intermetallic on various lead-free finish materials that have been stored at ambient condition for 2 yrs (6.3 × 10⁷ s) is investigated. The matte Sn plated leadframe (LF) had the needle-shaped whisker and the nodule-shaped whisker was observed on the semi-bright Sn plated LF. Both the Sn plated LFs had a same columnar grain structure and both whiskers were grown in connection with the scalloped intermetallic compound (IMC) layer. The morphology of the IMC layer is similar, regardless of the area which has whisker or not. On the Sn–Bi finish and bright Sn plated LF, hillock-shaped and sparsely grown branch-shaped whiskers were observed, respectively. The IMC grew irregularly under both the areas with or without whisker. The IMC growth along the Sn grain boundaries generated inner compressive stress at the plating layer. Atomic force microscopy (AFM) profiling analysis is useful for characterization the IMC growth on the Sn and Cu interface. The measured root mean square (RMS) values IMC roughness on semi-bright Sn, matte Sn, and bright Sn plated LF were 1.82 μm, 1.46 μm, and 0.63 μm, respectively. However, there is no direct relation between whisker growth and the RMS value. Two layers of η′-Cu₆Sn₅ were observed using field emission transmission electron microscopy (FE-TEM): fine grains and coarse grains existed over the fine grains.     

Whisker growth on surface treatment in the pure tin plating

Whisker behavior at various surface treatment conditions of pure Sn plating are presented. The temperature cycling test for 600 cycles and the ambient storage for 1 year was performed, respectively. From the temperature cycling test, bent-shaped whiskers were observed on matte and semibright Sn plating, and flower-shaped whisker on bright Sn plating. The bright Sn plating has smaller whiskers than the other types of Sn plating, and the whisker growth density per unit area is also lower than the others. After 1 year under ambient storage, nodule growth of FeNi42 lead frame (LF) was observed in some parts. The Cu LF showed about a 9.0 μm hillock-shaped whisker. This result demonstrated that the main determinant of whisker growth was the number of temperature cycling (TC) in the FeNi42 LF, whereas it was the time and temperature in the Cu LF. Also, whisker growth and shape varied with the type of surface treatment and grain size of plating.     

Improvement in high-temperature degradation by isotropic conductive adhesives including Ag–Sn alloy fillers

The reliability evaluation of Cu and Sn/Ni joined with isotropic conductive adhesives (ICAs) including Ag–Sn alloy fillers with or without Ag plating instead of Ag fillers was examined using tensile tests, electrical resistivity tests and microstructural observations. For an ICA, including Ag–Sn alloy fillers added to Sn–58wt%Bi fillers, the tensile strength was found to improve, but the electrical resistivity worsened with 150 °C heat exposure. An ICA, including, Ag–Sn alloy fillers with Ag plating, was able to maintain electrical resistivity after being subjected to 150 °C heat exposure. The Ag plating on the Ag–Sn fillers reacted with the Sn in the Ag–Sn fillers, leading to the joining of the fillers with each other though metallurgical connections, and the transformation of Ag into Ag₃Sn within a 1-h curing time at 150 °C, since the Ag plating was microscopic and active. After heat exposure, the Sn distributed itself along the substrate/ICA interface by the diffusion of Sn though the connected fillers, and Cu₃Sn formed at the Cu/ICA interface, in contrast with the Ag–Sn alloy fillers without Ag plating.     

Numerical and experimental analysis of the Sn3.5Ag0.75Cu solder joint reliability under thermal cycling

The Sn3.5Ag0.75Cu (SAC) solder joint reliability under thermal cycling was investigated by experiment and finite element method (FEM) analysis. SAC solder balls were reflowed on three Au metallization thicknesses, which are 0.1, 0.9, and 4.0 μm, respectively, by laser soldering. Little Cu–Ni–Au–Sn intermetallic compound (IMC) was formed at the interface of solder joints with 0.1 μm Au metallization even after 1000 thermal cycles. The morphology of AuSn₄ IMC with a small amount of Ni and Cu changed gradually from needle- to chunky-type for the solder joints with 0.9 μm Au metallization during thermal cycling. For solder joints with 4 μm Au metallization, the interfacial morphology between AuSn₄ and solder bulk became smoother, and AuSn₄ grew at the expense of AuSn and AuSn₂. The cracks mainly occurred through solder near the interface of solder/IMC on the component side for solder joints with 0.1 μm Au metallization after thermal shock, and the failure was characterized by intergranular cracking. The cracks of solder joints with 0.9 μm Au metallization were also observed at the same location, but the crack was not so significant. Only micro-cracks were found on the AuSn₄ IMC surface for solder joints with 4.0 μm Au metallization. The responses of stress and strain were investigated with nonlinear FEM, and the results correlated well with the experimental results.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

Effects of width scaling and layout variation on dual damascene copper interconnect electromigration

Electromigration versus line width in the 0.12–10 μm range and the configuration of the via/line contact in dual damascene Cu has been investigated. There are two scenarios for width scaling impact on electromigration. One is the width < 1 μm region, in which the MTF shows a weak width dependence, except for the via-limited condition. The other is the width > 1 μm region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width > 1 μm), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width > 1 μm) is approximately 0.2 eV higher than that of the dominant surface transport (width  1 μm). The derived activation energies for grain-boundary and surface diffusion are obtained from Cu drift velocity under electromigration stressing. The mechanisms governing the electromigration lifetime of interconnects leads to via interconnect design rules for maximizing lifetime being identified.     

Properties of low temperature Sn–Ag–Bi–In solder systems

The metallurgical and mechanical properties of Sn–3.5 wt%Ag–0.5 wt%Bi–xwt%In (x = 0–16) alloys and of their joints during 85 °C/85% relative humidity (RH) exposure and heat cycle test (−40–125 °C) were evaluated by microstructure observation, high temperature X-ray diffraction analysis, shear and peeling tests. The exposure of Sn–Ag–Bi–In joints to 85 °C/85%RH for up to 1000 h promotes In–O formation along the free surfaces of the solder fillets. The 85°C/85%RH exposure, however, does not influence the joint strength for 1000 h. Comparing with Sn–Zn–Bi solders, Sn–Ag–Bi–In solders are much stable against moisture, i.e. even at 85 °C/85%RH. Sn–Ag–Bi–In alloys with middle In content show severe deformation under a heat cycles between −40 °C and 125 °C after 2500 cycles, due to the phase transformation from β-Sn to β-Sn + γ-InSn₄ or γ-InSn₄ at 125 °C. Even though such deformation, high joint strength can be maintained for 1000 heat cycles.     

Electrical and structural properties of hafnium silicate thin films

Thin (4 nm) hafnium silicate (HfO₂)_x(SiO₂)_1−x/SiO₂ gate stacks (0 < x < 1) grown by metal organic chemical vapour deposition (MOCVD) are investigated in this study. The focus is on extracting the optical constants, and hence bandgaps as well as dielectric constants. The VUV (vacuum ultraviolet) spectroscopic ellipsometry (VUV-SE) technique in the spectral range 140–1700 nm, together with current–voltage and capacitance–voltage techniques were used for studying the optical and electrical properties of the layers, respectively. The bandgap was found to increase from 5.24 eV for HfO₂ to 6 eV for Hf-silicate with 30% Hf. The permittivity was reduced from 21 for HfO₂ layers to 8 for Hf-silicate with x = 0.3. The results suggest that the optimal Hf content is above 0.6, for which the permittivity higher than 10 can be achieved.     

Effects of process conditions on reliability, microstructure evolution and failure modes of SnAgCu solder joints

In this study, microstructure evolution at intermetallic interfaces in SnAgCu solder joints of an area array component was investigated at various stages of a thermal cycling test. Failure modes of solder joints were analyzed to determine the effects of process conditions on crack propagation. Lead-free printed-circuit-board (PCB) assemblies were carried out using different foot print designs on PCBs, solder paste deposition volume and reflow profiles. Lead-free SnAgCu plastic-ball-grid-array (PBGA) components were assembled onto PCBs using SnAgCu solder paste. The assembled boards were subjected to the thermal cycling test (−40 °C/+125 °C), and crack initiation and crack propagation during the test were studied. Microstructure analysis and measurements of interface intermetallic growth were conducted using samples after 0, 1000, 2000 and 3000 thermal cycles. Failures were not found before 5700 thermal cycles and the characteristic lives of all solder joints produced using different process and design parameters were more than 7200 thermal cycles, indicating robust solder joints produced with a wide process window. In addition, the intermetallic interfaces were found to have Sn–Ni–Cu. The solder joints consisted of two Ag–Sn compounds exhibiting unique structures of Sn-rich and Ag-rich compounds. A crystalline star-shaped structure of Sn–Ni–Cu–P was also observed in a solder joint. The intermetallic thicknesses were less than 3 μm. The intermetallics growth was about 10% after 3000 thermal cycles. However, these compounds did not affect the reliability of the solder joints. Furthermore, findings in this study were compared with those in previous studies, and the comparison proved the validity of this study.     

Degradation by Sn diffusion applied to surface mounting with Ag-epoxy conductive adhesive with joining pressure

Shear and tensile tests were carried out on joints made with an isotropic conductive adhesive (ICA) consisting of Ag and epoxy: Sn–Pb plated components mounted on printed boards and tensile bars consisting of Sn plated Ni and Cu joined under various joining pressures. After 150 °C–100 h, shear strength degraded to 72% and Sn in the plating diffused slightly to the Ag fillers in the ICA for the component mounting. High joining pressure increased the initial tensile strength and volume percentage of Ag fillers in the ICA. After 150 °C–100 h, tensile strengths for all joining pressures degraded on average to 36% of the initial strengths. In the case of low joining pressures, an Ag–Sn intermetallic was formed at only the Ag–Sn contact points of the Sn/ICA interface; leading to reproducibility of the component mounting. The difference of degradation ratios between the mounted components and tensile bars could be explained by the offset of the Sn–Pb area at the component/ICA interface.     

Investigation of Sn Whisker Growth in Electroplated Sn and Sn-Ag as a Function of Plating Variables and Storage Conditions

Sn whiskers are becoming a serious reliability issue in Pb-free electronic packaging applications. Among the numerous Sn whisker mitigation strategies, minor alloying additions to Sn have been proven effective. In this study, several commercial Sn and Sn-Ag baths of low-whisker formulations are evaluated to develop optimum mitigation strategies for electroplated Sn and Sn-Ag. The effects of plating variables and storage conditions, including plating thickness and current density, on Sn whisker growth are investigated for matte Sn, matte Sn-Ag, and bright Sn-Ag electroplated on a Si substrate. Two different storage conditions are applied: an ambient condition (30°C, dry air) and a high-temperature/high-humidity condition (55°C, 85% relative humidity). Scanning electron microscopy is employed to record the Sn whisker growth history of each sample up to 4000 h. Transmission electron microscopy, x-ray diffraction, and focused ion beam techniques are used to understand the microstructure, the formation of intermetallic compounds (IMCs), oxidation, the Sn whisker growth mechanism, and other features. In this study, it is found that whiskers are observed only under ambient conditions for both thin and thick samples regardless of the current density variations for matte Sn. However, whiskers are not observed on Sn-Ag-plated surfaces due to the equiaxed grains and fine Ag₃Sn IMCs located at grain boundaries. In addition, Sn whiskers can be suppressed under the high-temperature/high-humidity conditions due to the random growth of IMCs and the formation of thick oxide layers.     

Metallization of microvias by sputter-deposition

In high-density interconnection technologies the size of via holes significantly effects the space available for component assembly. Commonly used CO₂ lasers do not produce microvias small enough for future demands. In this paper we investigate metallization of UV-laser drilled microvias by magnetron sputtering.The core material of the test boards was a copper-clad FR-4 laminate. The boards were coated with two types of nonphotoimageable liquid dielectrics. A thin chrome layer (0.1 μm) with a subsequent copper layer (3 μm) or copper layer without any intermediate chrome layer was sputtered onto the surfaces and within the microvias. Copper was electrolytically grown onto the sputtered metal layers. In fine lines the adhesion of the metallic layer to the core material is essential. Our earlier studies have shown that chrome has good adhesion to epoxy and it is used as a seeding layer between epoxy and sputtered copper.The purpose of our research is to assess the usefulness of sputtering techniques for metallizing small vias and to find a combination of dielectric material, technologies for microvia formation and plating for achieving reliable microvia connections. Microvias were analyzed after every process stage by means of a microscope and a scanning electronic microscope.     

Characteristics of Sn8Zn3Bi solder joints and crack resistance with various PCB and lead coatings

Reliability of QFP (quad flat package) solder joints after thermal shock was investigated for PCB’s and connecting leads plated with several different alloy coatings before soldering. Sn–8 wt%Zn–3 wt%Bi (hereafter, Sn–8Zn–3Bi) was selected as a solder, and FR-4 PCB’s finished with Cu/Sn, Cu/OSP and Cu/Ni/Au were used as substrates. The leads of the QFP were Cu plated with Sn–10 wt%Pb, or Sn, or Sn–3 wt%Bi. The QFP chips were mounted on the substrates using a Sn–8Zn–3Bi solder paste and reflowed in air atmosphere. The pull strength and microstructure for the soldered leads of QFP were evaluated before and after thermal shock testing. The leads plated with Sn or Sn–3Bi showed approximately 40–50% higher pull strength than the reference value of a Sn–37%Pb solder joint for all PCB-finishes. However, in the case of leads coated with Sn–10Pb, the pull strength of the leads soldered to a Sn-finished PCB was 21% lower than the reference value. In microstructure analysis of the joints with Sn–10Pb-plated leads, cracks were found along the bonded interface for Sn-finished PCB. The cracks were believed to start from the low melting temperature phase, 49.38 wt% Pb–32.58 wt%Sn–18.03 wt%Bi, found around the crack, and then propagated through Cu–Zn intermetallic compound. Meanwhile, even when using Sn–10Pb-plated leads, the PCB’s finished with Cu/Ni/Au coating had about 30% higher strength than the reference value, and cracks were hardly found on the soldered joint. Thus, even with Sn–10Pb-plated leads the Cu/Ni/Au-finished PCB’s were evaluated to be as reliable as the reference joint.     

Evaluation of displacement rate effect in shear test of Sn–3Ag–0.5Cu solder bump for flip chip application

An experimental investigation was combined with a non-linear finite element analysis using an elastic–viscoplastic constitutive model to study the effect of ball shear speed on the shear forces of flip chip solder bumps. A solder composition used in this study was Sn–3mass%Ag–0.5mass%Cu. A low cost bumping process has been employed using electroless Ni and immersion Au followed by solder paste stencil printing. A thin layer of intermetallic compound, (Ni_1−xCu_x)₃Sn₄, was formed by the reaction between the solder and electroless Ni with a thickness of about 1.4 μm, while some discontinuous (Cu_1−yNi_y)₆Sn₅ particles were also formed at the interface. The compositions of the resulting compounds were identified using energy dispersive spectrometer (EDS) and electron microprobe analysis (EPMA). Shear tests were carried out over a shear speed range from 20 to 400 μm/s at a shear ram height of 20 μm. The shear force was observed to linearly increase with shear speed and reach the maximum value at the fastest shear speed in both experimental and computational results. The optimum shear speeds for the shear test of solder bumped flip chip were recommended to be not exceeding 200 μm/s. The failure mechanisms were discussed in terms of von Mises stresses and plastic strain energy density distributions.     

Microstructure evolution of the Sn–Ag–y%Cu interconnect

The lead free Sn–Ag–y%Cu (y = 0.0, 0.5, 1.0 and 2.0) interconnect interfacial microstructures and the microstructure evolution under thermal treatment (isothermal aging, 150 °C/1000 h) were studied in detail by using surface microetching microscopy and cross section microscopy. The corresponding mechanical and reliability behaviors were evaluated by performing shear test and fracture mode analysis before and after the thermal treatment. The results indicate: (i) The interconnects could have different microstructures and intermetallic compound (IMC), depending on the Cu content. The Cu–Sn IMC could have microstructures that were clusters or protrusion-like, Augustine grass leaf-like, scissor-like, tweezers-like, etc. (ii) Ag₃Sn IMCs were not observed at time zero for any interconnect groups, but they occurred after the aging for all groups. The Ag₃Sn IMC could have different microstructures, again depending on Cu content. For low Cu content, the Ag₃Sn IMCs were granules or nodules; for higher Cu content, Ag₃Sn IMCs were plate-like. (iii) The growth of Ag₃Sn plates was promoted by the growth of Cu–Sn IMCs, but indirectly linked to the Cu content. (iv) High Cu content (1.0 wt% and higher) could degrade the mechanical and reliability performances of the LF interconnect by providing a brittle joint, which was mainly achieved through the substantial growth of Cu–Sn IMCs and Ag₃Sn plates.     

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Distribution of interface states at the emitter–base heterojunctions in heterostructure bipolar transistors (HBTs) is characterized by using current–voltage characteristics using sub-bandgap photonic excitation. Sub-bandgap photonic source with a photon energy E_ph which is less than the energy bandgap E_g (E_g,GaAs = 1.42, E_g,AlGaAs = 1.76 eV) of emitter, base, and collector of HBTs, is employed for exclusive excitation of carriers only from the interface states in the photo-responsive energy range at emitter–base heterointerface. The proposed method is applied to an Al_0.3Ga_0.7As/GaAs HBT (A_E = W_E × L_E = 250 × 100 μm²) with E_ph = 0.943 eV and P_opt = 3 mW. Extracted interface trap density D_it was observed to be D_it,max  4.2 × 10¹² eV⁻¹ cm⁻² at emitter–base heterointerface.     

The formation and growth of intermetallic compounds and shear strength at Sn–Zn solder/Au–Ni–Cu interfaces

The microstructures and shear strength of the interface between Sn–Zn lead-free solders and Au/Ni/Cu interface under thermal aging conditions was investigated. The intermetallic compounds (IMCs) at the interface between Sn–Zn solders and Au/Ni/Cu interface were analyzed by field emission scanning electron microscopy and transmission electron microscopy. The results showed the decrease in the shear strength of the interface with aging time and temperature. The solder ball with highly activated flux had about 8.2% increased shear strength than that with BGA/CSP flux. Imperfect wetting and many voids were observed in the fracture surface of the latter flux. The decreased shear strength was influenced by IMC growth and Zn grain coarsening. In the solder layer, Zn reacted with Au and then was transformed to the β-AuZn compound. Although AuZn grew first, three diffusion layers of γ-Ni₅Zn₂₁ compounds were formed after aging for 600 h at 150 °C. The layers divided by Ni₅Zn₂₁ (1), (2), and (3) were formed with the thickness of 0.7 μm, 4 μm, and 2 μm, respectively.     

The effects of buffer thickness on GaAs MESFET characteristics: channel–substrate current, drain breakdown, and reliability

The effects of thickness in metal–semiconductor field effect transistor (MESFET) GaAs buffer on the device electrical performance and reliability have been investigated. Devices studied are 0.8-μm-gate GaAs MESFETs at different buffer thickness of 0.5 and 0.3 μm from similar MBE-grown processes. Three-terminal off-state breakdown measurements indicate that a substantial enhancement in the observed breakdown current for thinner-buffer MESFETs is attributed to the drain–source leakage or breakdown through the channel–substrate interface while the device is at pinch-off. DC and RF biased stress lifetests up to 323 °C channel temperature have been performed to accelerate the degradation mechanisms. It is found that the device degradation rate has little dependence on buffer thickness when stressed at a reversed gate–drain voltage below 70% of its breakdown threshold. The differences grow rapidly when biased close to the breakdown field because of the development of channel–substrate current in thinner buffer materials.     

Effects of fourth alloying additive on microstructures and tensile properties of Sn–Ag–Cu alloy and joints with Cu

The effects of the fourth elements, i.e., Fe, Ni, Co, Mn and Ti, on microstructural features, undercooling characteristics, and monotonic tensile properties of Sn–3 wt.%Ag–0.5 wt.%Cu lead-free solder were investigated. All quaternary alloys basically form third intermetallic compounds in addition to fine Ag₃Sn and Cu₆Sn₅ and exhibit improved solder structure. The precipitates of Sn–3Ag–0.5Cu (–0.1 wt.%X; X=Ni, Ti and Mn) alloy are very fine comparing with the other alloys. The effective elements for suppressing undercooling in solidification are Ti, Mn, Co and Ni. All quaternary bulk alloys exhibit similar or slightly larger tensile strengths; especially Mn and Ni can improve elongation without degrading strength. The interfacial phases of Sn–3Ag–0.5Cu (–0.1 wt.%X; X=Fe, Mn and Ti)/Cu joints are typical Cu₆Sn₅ scallops. Sn–3Ag–0.5Cu (–0.1 wt.%X; X=Ni and Co)/Cu joints form very fine Sn–Cu–Ni and Sn–Cu–Co scallops at interface. The Cu/Sn–3Ag–0.5Cu–0.1Ni/Cu joint exhibits improved tensile strength prior to thermal aging at 125 and 150 °C. The fracture surface of Cu/Sn–3Ag–0.5Cu/Cu joint exhibits mixture of ductile and brittle fractures, while Cu/Sn–3Ag–0.5Cu (–0.1X; X=Ni and Co)/Cu joints exhibit only brittle fracture at interface. The Sn–3Ag–0.5Cu–0.1Ni alloy is more reliable solder alloy with improved properties for all tests in the present work.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.