Improved flash cell performance by N2O annealing ofinterpoly oxide

In this letter, we report the effects of N₂O annealing of interpoly oxide on flash cell performance. It is demonstrated that by adding an N₂O anneal after interpoly oxide formation, improved cycling endurance is achieved. The program and erase efficiencies are also improved significantly, compared to the control cell without N₂O anneal. The cells with N₂O anneal show higher cell current (i.e., drain current), which can be ascribed to a lower threshold voltage and higher transconductance, compared to the control cell     

A high-endurance low-temperature polysilicon thin-film transistorEEPROM cell

A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N₂O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N₂O-plasma oxide with good charge-to-breakdown (Qbd) characteristics     

High quality interpoly-oxynitride grown by NH3nitridation and N2O RTA treatment

In this letter, a method to grow high quality interpolysilicon-oxynitride (interpoly-oxynitride) film is proposed. Samples, nitridized by NH₃ with additional N₂O annealing and CVD TEOS deposited on poly-oxynitride (poly-I) with RTA N ₂O oxidation, show excellent electrical properties in terms of very high electric breakdown field, low leakage current, high charge to breakdown, and low electron trapping rate. This novel film is a good candidate for an interpoly dielectric of future high density EEPROM and flash memory devices     

Characterization of the triple-gate flash memory endurance degradation mechanism

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash mem-ory have been detected and analyzed using a tYV erasure method. Different from the commonly degradation phe-nomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in horn-shaped SuperFlash(R) does not occur in the triple-gate flash cell. This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash(R) cell. Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.     

三栅 SuperFlash闪存的耐久性退化机理特性

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash memory have been detected and analyzed using a UV erasure method. Different from the commonly degradation phenomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in hornshaped SuperFlash does not occur in the triple-gate flash cell This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash cell Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

Reduction of leakage current in chemical-vapor-deposited Ta2O5 thin films by furnace N2O annealing

In this brief, we present a post-deposition annealing technique that employs furnace annealing in N₂O (FN₂O) to reduce the leakage current of chemical-vapor-deposited tantalum penta-oxide (CVD Ta₂O₅) thin films. Compared with furnace annealing in O₂ (FO) and rapid thermal annealing in N ₂O (N₂O), FN₂O annealing proved to have the lowest leakage current and the most reliable time-dependent dielectric breakdown (TDDB)     

MOS characteristics of ultrathin NO-grown oxynitrides

In this paper, we report for the first time, the growth of high quality ultrathin oxynitrides formed by nitridation of SiO₂ in nitric oxide (NO) ambient using in-situ rapid thermal processing (RTP). This process is highly self-limited compared with N₂O oxidation of silicon. A significant improvement in the interface endurance and charge trapping properties, under constant current stress, compared to pure O₂-grown and N₂O-grown oxides is observed. The NO growth process will have a great impact on future CMOS and EEPROM technologies     

A 1 Mb EEPROM with MONOS memory cell for semiconductor diskapplication

A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm² with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.     

A versatile stacked storage capacitor on FLOTOX cell for megabitNVRAM's

A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm ² NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 10⁶ cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

The TEOS oxide deposited on phosphorus in-situ/POCl3doped polysilicon with rapid thermal annealing in N2O

This work presents a TEOS oxide deposited on the phosphorus-in-situ doped polysilicon with rapid thermal N₂O annealing. The oxide exhibits good electron trapping characteristics with a charge-to-breakdown (Q_bd) up to 110 C/cm². It is due to the good polysilicon/oxide interface morphology obtained by replacing POCl₃ doping with in-situ doping and the rapid thermal annealing in N₂O. In addition, the N₂O annealing densifies the deposited oxide and incorporates nitrogen into the oxide and at the polysilicon/oxide interface, thus improving the electrical characteristics     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

High field stressing effects on the split N2O grown thingate dielectric by rapid thermal processing

Highly reliable thin oxynitride layers of very good Si-SiO₂ interface endurance were grown on silicon wafers with a split N ₂O cycle (N₂O/O₂/N₂O) employing rapid thermal processing (RTP). Excellent electrical characteristics with reduced positive charge generation, electron trapping and/or interface state generation were achieved under high field stressing compared to pure N₂O dielectric     

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.     

Improvement of charge trapping characteristics ofN2O-annealed and reoxidized N2O-annealed thinoxides

It is found that increasing N₂O annealing temperature and time monotonically reduces electron trapping in the resulting oxides. The improvement increases with oxide thickness. Reoxidation does not enhance but reduces the improvement. The behavior is different from and simpler to understand than that after NH₃ annealing, apparently due to the absence of deleterious hydrogen. Hole trapping and interface trap generation are also suppressed by N₂O annealing, though an optimum anneal condition may exist. Charge to breakdown exhibits modest improvement consistent with reduced electron trapping     

A design of experiment analysis of serial EEPROM endurance

The results of a study using a design of experiments approach to examine the effects of environmental operating conditions on serial EEPROM endurance are presented. The conditions studied in the experiment were operating temperature, applied voltage, device type, array usage, write cycles per day, data pattern, and write pulse width. An ANOVA table showing the significant effects and an estimation of the value of the effects using an error minimization technique is presented. While the techniques presented are relatively simple, they may be useful as a quick check of acceleration effects in EEPROM endurance cycling, without the use of extensive factorial experiments. The results show temperature, array size and voltage to be the most important effects on EEPROM endurance cycling. The temperature effect matches other published data.