The effects of fixed bulk charge on the thermal noise in metal-oxide-semiconductor transistors

The theory of the thermal noise due to channel conductance fluctuation is extended for insulated gate (MOS) field effect transistors with the gate voltage induced channel structure by including the bulk charge from the ionized impurities in the semiconductor substrate. In the saturation range of the drain characteristics, the theory shows thatR_{gns} g_{ms} geq 2/3, where the equality condition corresponds to the previously obtained result for an intrinsic or chemically pure semiconductor substrate. Satisfactory correlations between theory and experimental measurements are obtained for both P-channel and N-channel silicon devices with either a thin oxide (2000A) or a thick oxide (6200 and 8400A) gate.     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

The silicon-silicon dioxide system

Study of the silicon-silicon dioxide system as a junction between a nearly ideal semiconductor and insulator has aroused both scientific and technological interest. Surface phenomena associated with this system are influenced by contamination and imperfections in the oxide, impurity redistribution in the silicon near the oxide, and finally by additional electronic energy states at the oxide-silicon interface. Over the past few years, the MOS (metal-oxide-semiconductor) approach has been highly developed and is the principal tool for the investigation of silicon surface phenomena. The theory of the ideal MOS capacitor is reviewed followed by a study of its use in the analysis of surface effects. Finally, the three-way relationship of the effect of oxide formation conditions and heat treatment on the properties of the oxidized silicon surface, and the subsequent influence of the properties of this surface on semiconductor device parameters is reviewed.     

Silicon nitride as a mask in phosphorus diffusion

By means of tracer and activation experiments it is shown that during phosphorus diffusion in silicon nitride diffusion profiles are produced, which are very similar to the profiles in silicon dioxide processed in the same experiment. When oxygen was used as part of the carrier gas as is customary in semiconductor technology, a glass was produced in both cases which consisted of SiO₂ and P₂O₅ and whose identity was proved by i.r. absorption and determination of the refractive index. When the medium does not contain oxygen, part of the nitride is transformed to silicon phosphide which is incorporated in the glass or escapes at higher temperatures. When oxygen is present, the silicon phosphide occurs briefly in an intermediate reaction. In this way the normal, slow oxidation of the nitride is accelerated and phosphorus pentoxide acts as a catalyst. The analogous formation of glass from oxide and nitride is the reason why silicon nitride exhibits a similar masking effect as silicon dioxide in phosphorus diffusion, even though it masks better than silicon dioxide against the diffusion of a number of other elements.     

氧化物薄膜晶体管刻蚀阻挡层PECVD沉积条件研究

为实现氧化物TFT(Indium Gallium Zinc Oxide Thin Film Transistor,IGZO TFT)特性的最优化,采用I-V数据和SEM(Scanning Electron Microscope)图片研究蚀阻挡层(Etch-Stop Layer,ESL)沉积条件与氧化物TFT特性的关系。通过调整沉积温度、正负极板间距、压力和功率,分析了PECVD沉积ESL SiO2的成膜规律,并对所得到的TFT进行了特性分析。发现ESL膜层致密性过差时,后期高温工艺会造成水汽进入IGZO半导体膜层,从而引起TFT特性恶化。而采用高温、高压力等方法取得高致密性的ESL膜层由于高强度等离子体对IGZO本体的还原反应也会致使TFT特性劣化。结果表明,在保证膜层致密性前提下,等离子体对IGZO本体伤害最小的ESL沉积条件才是最优化的ESL沉积条件。     

A theory of the effect of impurities on the yield stress of silicon crystals

A theoretical model that attributes the effect of mobile neutral impurities on the special features of strain in semiconductor crystals to the phenomenon of dynamic aging of dislocations is suggested. Dependences of the upper yield stress on the concentration of impurity atoms, the strain rate, and other parameters are calculated. The results of calculations are consistent with experimental data for silicon.     

Comparison between CVD and thermal oxide dielectric integrity

Low-pressure chemical vapor deposited (CVD) oxide and thermal oxide of identical thickness (360 A) are compared. CVD oxide exhibits much lower incidence of breakdown at the electric fields below 8 MV/cm, in agreement with the notion that the breakdown is largely due to the incorporation of impurities in the silicon substrate into the oxide during thermal oxidation. Furthermore, CVD oxide shows identical IV characteristics as thermal oxide and significantly lower rates of electron and hole trapping. Based on these results, CVD oxide may be an intriguing candidate for thin dielectric applications.     

Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd₂O₃) from a silicon oxide (SiO₂) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).     

Changes in the state of phosphorus atoms in the silicon lattice as a result of interaction with radiation defects

Interaction of radiation defects with phosphorus atoms in silicon crystals subjected to electron irradiation and thermal treatments was studied under conditions of various degrees of supersaturation with respect to the equilibrium concentration of impurities and point defects. It is shown that, in the course of silicon irradiation, the electron-dose dependences of the phosphorus concentration at the lattice sites (P_s) level off (tend toward a constant value). This constant value is governed by the irradiation temperature. The stages of recovery of the concentration P_s as a result of heat treatments correlate with temperature intervals of dissociation of the vacancy complexes. The results indicate that there are two processes. One process involves the interaction of dopant atoms with silicon self-interstitials and the emergence of interstitial complexes; i.e., this process corresponds to the radiation-stimulated decomposition of a supersaturated solution of an impurity as a result of point-defect generation and ionization. The other process consists in the recombination of interstitial impurities with vacancies at sufficiently high temperatures or in the annihilation of vacancies released during heat treatments with interstitial atoms incorporated into composite defect complexes with the involvement of phosphorus atoms.     

Confocal Raman Spectroscopy of α‐Sexithiophene: From Bulk Crystals to Field‐Effect Transistors

We report confocal micro‐Raman spectra of the organic semiconductor α‐sexithiophene (T6) on bulk crystals and on thin films grown on technologically relevant substrates and devices. We show that the two polymorphs, which are clearly identified by their lattice phonon spectra, may coexist as physical impurities of one inside the other in the same crystallite. Spatial distribution of the two phases is monitored by Raman phonon mapping of crystals grown upon different conditions. Raman microscopy has then been extended to T6 thin films grown on silicon oxide wafers. We identify the crystal phase in thin films whose thickness is just 18 nm. The most intense total‐symmetric Raman vibration is still detectable for a two‐monolayer thick film. Comparative analysis between micro‐Raman and AFM of T6 thin films grown on field effect transistors shows that electrode‐channel steps favour the nucleation and growth of T6 molecules on the substrate, at least below 50 nm.     

Simox technology and its application to CMOS LSIS

SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.     

中子辐照单晶硅与激光退火制备SOI结构的研究

SOI材料在制作高速、抗辐照电路、复合功能器件以及实现三维集成电路等方面有着重要的应用前景.实现SOI结构有多种途径:除蓝宝石外延(SOS)工艺外,还有多晶硅的激光或电子束熔化再结晶、石墨条加热再结晶和在单晶硅中大剂量深注入氧形成隔离层等方法.利用中子辐照使单晶硅损伤,得到了绝缘层衬底,然后以激光退火消除表面层损     

A novel sacrificial gate stack process for suppression of boronpenetration in p-MOSFET with shallow BF2-implantedsource/drain extension

A novel process flow employing a sacrificial tetraethyl orthosilicate/polycrystalline silicon (TEOS/poly-Si) gate stack is proposed for fabricating fluorine-enhanced-boron-penetration-free p-channel metal oxide semiconductor field effect transistors (p-MOSFET's) with shallow BF₂-implanted source/drain (S/D) extension. With the presence of the sacrificial TEOS/poly-Si gate stack as the mask during the shallow BF₂ implant, the incorporated fluorine atoms are trapped in the sacrificial TEOS top layer and can be subsequently removed. The new process thus offers a unique opportunity of achieving an ultra shallow S/D extension characteristic of the BF₂ shallow implant, while not suffering from any fluorine-enhanced boron penetration normally accompanying the BF₂ implant. Excellent transistor performance with improved gate oxide integrity has been successfully demonstrated on p-MOSFET's fabricated with the new process flow     

伯克利短沟道绝缘栅场效应晶体管模型的研究进展

随着金属氧化物半导体(MOS)集成电路工艺的飞速发展,体硅金属氧化物半导体场效应晶体管(MOSFET)模型经历了从物理到经验,最后到半经验物理的转变.介绍了以阈值电压和反转电荷为建模基础的伯克利短沟道绝缘栅场效应晶体管模型(BSIM),以及该模型中阈值电压、饱和电流和电容的基本建模理论.回顾了近年来体硅MOSFET BSIM的研究进展,着重从各种模型的优缺点、建模机理和适用范围方面分析了4种最有代表性的BSIM,即BSIM3v3,BSIM4,BSIM5和BSIM6.从模型的发展历史可以看出模型是随着MOSFET尺寸的缩小而不断完善和发展的.最后,对体硅MOSFET的模型发展趋势进行了展望.     

Standardized terminology for oxide charges associated with thermally oxidized silicon

Standarized terminology for oxide charges associated with the thermally oxidized silicon system is presented. This terminology is recommended by a committee established by the Electronics Division of the Electrochemical Society and the IEEE Semiconductor Interface Specialists Conference. All engineers and scientists concerned with oxide charges in silicon semiconductor applications are urged to adopt this terminology.     

Controlling Electron Mobility of Strongly Coupled Organic Semiconductors in Mirrorless Cavities

Recent experiments on the strong light-matter coupling between an organic semiconductor and a plasmonic mode propose an unconventional way to enhance conductivity. Herein, it is shown that mirrorless cavities can boost conductivity by simply structuring the refractive indices of the multilayers in a commercially available metal oxide semiconductor field effect transistor (MOSFET). Perylene diimide (an organic semiconductor dye) molecules are deposited on a MOSFET device. The refractive index mismatch between the silicon/silicon dioxide/dye/air results in light confinement. The frequency of this confined light is tuned by changing the thickness of the organic semiconductor layer. Interestingly, an increase in electron mobility was observed once the electronic transition of the dye molecules and the second-order cavity mode enter into the strong coupling regime. Whereas resonance tuning to the first-order mode does not affect the electron transport. Here, the system is still in a weak coupling regime. These results are further correlated by experimental dispersion measurements and supported with transfer matrix simulations. The increase in electron mobility is not large due to high dissipation or low-quality factors of the cavity modes. However, the mirrorless configuration presented here may offer a simpler way of boosting the properties of functional materials.     

The effect of high temperature annealing on the spatial variation of bulk lifetime near the SiSiO2 interface

In this paper, the effect of high temperature N₂ annealing at 1100°C on the minority carrier lifetime in the bulk of the silicon close to the SiSiO₂ interface has been investigated for dry thermal oxides and TCE oxides. This annealing results in substantial reduction of lifetime for dry thermal oxides and the same annealing process enhances the lifetime for TCE oxides. The annealing-affected region in silicon near the interface was scanned by computing lifetime as a function of distance from the SiSiO₂ interface, using the Zerbst method with a suitable modification. The smaller values of lifetime observed near the SiSiO₂ interface have been correlated with stacking faults whose electrical activity seems to be significantly controlled by metallic impurities. A mechanism (supported by the experimental results) is suggested for the lifetime change due to annealing. The influx of metallic impurities coming from the annealing ambient seems to be decreasing the lifetime of carriers in silicon under dry thermal oxides, whereas, for the TCE oxides, we postulate that chlorine incorporated in the oxides prevents this influx and further also helps in the deactivation of existing metallic impurities in the silicon.     

The Effect of the Ionizing Radiation Intensity on the Response of MOS Structures

Semiconductors - The effect of the intensity of ionizing radiation on the volume charge and surface-state density of metal—oxide—semiconductor (MOS) structures with thin gate silicon...     

Silicon doping by nuclear transmutation

This paper describes, from the view of nuclear physics and radiochemistry, the mode of operation in doping semiconductor silicon with phosphorus by neutron irradiation. In addition to precise control of the irradiation fluence, this includes control of neutron-flux distribution, self-shielding and radioactive products from the silicon matrix and the surface impurities. The accuracy of the resistivity values achieved by this method is better than ± 5% at the predicated value. The good homogeneity of the dopant distribution is shown by the results of location-resolving resistivity measurements as well as by the breakdown radiation emitted by diodes. Neutron-bombarded homogeneously doped silicon (NBH-silicon) is used for routine manufacture of multi-diode vidicons and power devices.