Material and electrical properties of electroless Ag-W thin film

Thin Ag-W films were prepared on Si (100) substrate and on metal (Ag and Co) seed layers by electroless technology for ULSI applications. The thin film electrical and physical parameters were studied as a function of the film composition. The thin film composition depends on the electroless bath formula. The role of the tungsten in silver matrix was studied via measurements of the film microhardness and thermal stability as function of the composition. The Ag-W films, thicker than 200 nm, exhibited a specific electrical resistivity of about 2μΩ* and a reflectivity larger than 90%. These films have not corroded in air at temperatures up to 200°C (thermal stable). Therefore, we assume that silvertungsten films can be used for applications where reliable conducting thin films is required, such as packaging and interconnects for microelectronics.     

Reduced thermal strain in flip chip assembly on organic substrateusing low CTE anisotropic conductive film

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances, resulting in a high performance and cost-competitive packaging method. This paper describes the usefulness of low cost flip-chip assembly using electroless Ni/Au bump and anisotropic conductive films on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed as a low cost bumping method. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with Ni₃P precipitation above 300°C causes an increase of hardness and an increase of the intrinsic stress. As interconnection material, modified ACFs composed of nickel conductive fillers for conductive fillers, and nonconductive fillers for modification of film properties, such as coefficient of thermal expansion (CTE), were formulated for improved electrical and mechanical properties of ACF interconnection. Three ACF materials with different CTE values were prepared and bonded between Si chips and FR-4 boards for the thermal strain measurement using moire interferometry. The thermal strain of the ACF interconnection layer, induced by temperature excursion of 80°C, was decreased according to the decreasing CTEs of ACF materials. This result indicates that the thermal fatigue life of ACF flip chip assembly on organic boards, limited by the thermal expansion mismatch between the chip and the board, could be increased by low CTE ACF     

Manufacturing of Cu/electroless nickel/Sn-Pb flip chip solder bumps

A process for manufacturing Cu/electroless Ni/Sn-Pb solder bump is discussed in this paper. An attempt to replace zincation with a Cu film as an active layer for the electroless Ni (EN) deposition on Al electrode on Si wafer is presented. Cu/electroless Ni is applied as under bump metallurgy (UBM) for solder bump. The Cu film required repeated etches with nitric acid along with activation to achieve a satisfactory EN deposit. Fluxes incorporating rosin and succinic acid were investigated for wetting kinetics and reflow effectiveness of the electroplated solder bump. The solder plating current density and the reflow condition for achieving solder bumps with uniform bump height were described. The Cu/EN/Sn-Pb solder system was found to be successfully produced on Al terminal in this study that avoids using zincating process     

Preparation and Temperature Cycling Reliability of Electroless Ni(P) Under Bump Metallization

The reliability of electroless Ni(P) under-bump metallization (UBM) was evaluated via temperature cycling and solder bump shear strength tests. Commercial diodes and dummy dies fabricated in-house were used as substrates for the electroless Ni(P) UBM deposition. Solder bumps were formed after reflowing eutectic 63Sn37Pb solder foils over the Ni(P) UBM. The solder bump shear strength was measured before and after different temperature cycling. The results from this study showed that the UBM thickness and dimension had important effects on the solder bump shear strength and reliability. Both the larger UBM dimension and larger UBM thickness tended to induce higher stress in the UBM, which resulted in the lower solder bump shear strength and lower temperature cycling reliability. A better UBM structure solution for high current electronic packaging application is indicated in this paper     

Residual stress in silicon nitride films

The mechanical stress caused by Si₃N₄ films on (111) oriented Si wafers was studied as a function of the Si₃N₄ film thickness, deposition rate, deposition temperature and film composition. The Si₃N₄ films were prepared by the reaction of gaseous SiH₄ and NH₃ in the temperature range 700–1000°C. The curvature of the Si substrates caused by the Si₃N₄. films is related to the film stress; the substrate curvature was measured by an optical interference technique. The measured Si₃N₄. film stress was found to be highly tensile with a magnitude of about 10¹⁰ dynes/cm². For the thickness range of 2000–5000Å, there was no change in the measured stress. The total film stress was observed to decrease for decreasing deposition rate and increasing deposition temperature. A large change in film stress was observed for films containing excess Si; the stress decreased with increasing Si content. Based on published values for the thermal expansion coefficients for Si and Si₃N₄, a published value for Young’s Modulus for Si₃N₄, and the measured total stress values, a consistent argument is developed in which the total stress consists of a compressive component due to thermal expansion coefficient mismatch and a larger tensile intrinsic stress component. Both the thermal and intrinsic stress components vary with film deposition temperature in directions which decrease the total room temperature stress for higher deposition temperatures.     

Improvement of reliability for high-ohmic Cr–Si thin film resistors in a heat and humid environment: Removing moisture source by electrocatalytic decomposition of water

The reliability of high-ohmic Cr–Si thin film resistors in a heat and humid (HH) environment is often guaranteed by packaging materials as protection layers. Our previous study shows that Cr–Si–Ni film has a better performance in HH resistance than Cr–Si film in the same experimental conditions, and the proposed hypothesis that the electrocatalytic activity of Ni in the resistive film leads to water decomposition is considered as the reason behind it. In addition, NiMo alloy film is reported to have a better electrocatalytic activity on water decomposition than Ni film. So an issue arises: will the Cr–Si film co-doped by both Ni and Mo have a better performance in HH resistance than Cr–Si film only doped by Ni? In our current full paper, Cr–Si–Ni–Mo and Cr–Si–Ni films with low temperature coefficient of resistance (TCR) were prepared and compared in the same conditions to study their performance in a HH environment, which may address the raised issue from experimental data and further verify the proposed hypothesis. Possible reasons for the experimental results were discussed. If the proposed hypothesis is true, another way may be opened up to improve the reliability of high-ohmic Cr–Si resistors in a HH environment.     

Uniformity of an Electroless Plated Ni on a Pad Connected to Different Size Pads or a Pn Junction for Under Bump Metallurgy in a Flip-Chip Assembly

We investigated electroless Ni uniformity on Al metal pads connected to different size pads or a pn junction for under bump metallurgy in flip-chip assemblies. In an electrically isolated pad, Ni thickness decreased as the pad size decreased. Because of nonlinear diffusion of Pb²⁺ stabilizer in the plating solution, fewer electrons were supplied to the smaller pad than to the larger pad by an anodic oxidation reaction on the pad surface. In pads smaller than 50 mum square, the Ni thickness increased when connected to a 100 mum square pad. This increase might be caused by electrons flowing from the 100 mum square pad to the smaller pad to produce an equipotential for the connected pads. In addition, the Ni thickness was increased by electrical connection to an n-type Si in the presence of fluorescent light illumination for a pn junction area larger than 100 mum². For a pad connected to a p-type Si, however, Ni thickness decreased in comparison to that of an electrically-isolated pad, regardless of the light illumination or pn junction area. The change of Ni height on pads connected to the pn junction is attributable to photoelectrons injected into the n-type Si, or to electron-hole recombination in the p-type Si. These results indicate that the pads should be of the same size within a chip for better Ni uniformity. Moreover, blocking light during Ni electroless plating can eliminate Ni thickness differences due to an n-type Si connection.     

Electroless CoWP as a Diffusion Barrier between Electroless Copper and Silicon

In this work, an electroless CoWP film deposited on a silicon substrate as a diffusion barrier for electroless Cu and silicon has been studied. Four different Cu 120 nm/CoWP/Si stacked samples with 30, 60, 75, and 100 nm electroless CoWP films were prepared and annealed in a rapid thermal annealing (RTA) furnace at 300°C to 800°C for 5 min. The failure behavior of the electroless CoWP film in the Cu/CoWP/Si sample and the effect of CoWP film thickness on the diffusion barrier properties have been investigated by transmission electron microscopy (TEM), scanning electron microscopy (SEM), X-ray diffraction (XRD), and sheet resistance measurements. The composition of the electroless CoWP films was 89.4 at.% Co, 2.4 at.% W, and 8.2 at.% P, as determined by energy dispersive X-ray spectrometer (EDS). A 30 nm electroless CoWP film can prevent copper penetration up to 500°C, and a 75 nm electroless CoWP film can survive at least up to 600°C. Therefore, increasing the thickness of electroless CoWP films effectively increases the failure temperature of the Cu/CoWP/Si samples. The observations of SEM and TEM show that interdiffusion of the copper and cobalt causes the failure of the electroless CoWP diffusion barriers in Cu/CoWP/Si during thermal annealing.     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。     

Out-of-Plane Magnetic Anisotropy and Microwave Permeability of Magnetoelastic FeCoSiB Amorphous Thin Films

Theamorphous magnetoelastic Fe66Co17Si1B6 thin films have been deposited by dc magnetron sputtering. A lot of ＂nano-trenches＂ have been observed on the fdm surfaces by AFM. The permeability of amorphous Fe66COlTSilB6 thin films was measured within the frequency range of 0.6GHz-10.2 GHz. The ferromagnetic resonance frequency was found to be 1.2 GHz. MFM shows that the domain of thin film is a maze-type pattern, which indicates that an out-of-plane magnetic anisotropy exists. The out-of-plane anisotropy is believed due to the stress-induced magnetic anisotropy. It can be inferred that the internal stress is tensile stress and normal to the film plane. Index Terms     

Black Pad Susceptibility of the Electroless Ni Films on the Cu UBM

The occurrence of black pad in the electroless Ni film during the immersion gold process is related to the surface morphology of the Ni(P) film. A nonuniform distribution of the nodule size and curvature is the crucial factor. Large nodules with small surface curvatures had higher P concentration and did not corrode, while small nodules with large surface curvatures had lower P concentration and corroded. Experiments using different types of Cu substrates suggest that the Ni(P) film black pad susceptibility increased with the defect density and/or the residual stress in the underlying substrate. Annealing the Cu substrate before the electroless Ni plating greatly reduced the black pad formation.     

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects     

Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.     

Electrochemically deposited thin film alloys for ULSI and MEMS applications

Thin metal films can be electro-deposited for interconnect metallization and packaging. Electro-forming offers unique properties, such as excellent filling of high aspect ratio structures, unique compositions, low temperature processing and low stress films. Electroless forming offers also high selectivity. Binary and ternary metallic alloys, such as Ni, Co and Cu, alloyed with iron, phosphorous, boron and refractory metals have been demonstrated to form conducting layers, barriers, and corrosion protection layers. High quality very thin films, with thickness varied between 5 nm and 1 μm, have been demonstrated with good composition control. After reviewing the basic deposition mechanisms we focus on Co and Ni alloys with refractory metals (e.g., tungsten and molybdenum) and with phosphorous and/or boron. We present results of electroless deposition of CoWP as examples for an electrochemical process compatible with silicon technology. Finally we present a process outline for alloy deposition on silicon, or SiO₂, for MEMS applications.     

Uniaxial Ratchetting Behavior of Solder Alloys and Its Simulation by an Elasto-Plastic-Creep Constitutive Model

Ratchetting deformation occurring at solder joints in electronic packaging is a concern for electronic devices. Therefore, ratchetting deformation due to thermal cycling at solder joints should be simulated by structural analysis employing tools such as the finite-element method (FEM). However, simulation of ratchetting deformation is difficult, and little modeling to simulate ratchetting deformation accurately has been reported. This work experimentally examines uniaxial ratchetting deformation of Pb-free and Pb-containing solder alloys to elucidate the effect of rate on uniaxial ratchetting. An elasto-plastic-creep constitutive model is developed to simulate uniaxial ratchetting deformation. The constitutive model incorporates a method to determine the material constants simply from a small number of pure tensile tests and subsequent stress relaxation tests. Uniaxial ratchetting deformation of solder alloys was successfully simulated using this constitutive model and simple method for material constant determination.     

Interfacial reactions and compound formation of Sn-Ag-Cu solders by mechanical alloying on electroless Ni-P/Cu under bump metallization

Electroless Ni-P under bump metallization (UBM) has been widely used in electronic interconnections due to the good diffusion barrier between Cu and solder. In this study, the mechanical alloying (MA) process was applied to produce the SnAgCu lead-free solder pastes. Solder joints after annealing at 240°C for 15 min were employed to investigate the evolution of interfacial reaction between electroless Ni-P/Cu UBM and SnAgCu solder with various Cu concentrations ranging from 0.2 to 1.0 wt.%. After detailed quantitative analysis with an electron probe microanalyzer, the effect of Cu content on the formation of intermetallic compounds (IMCs) at SnAgCu solder/electroless Ni-P interface was evaluated. When the Cu concentration in the solder was 0.2 wt.%, only one (Ni, Cu)₃Sn₄ layer was observed at the solder/electroless Ni-P interface. As the Cu content increased to 0.5 wt.%, (Cu, Ni)₆Sn₅ formed along with (Ni, Cu)₃Sn₄. However, only one (Cu, Ni)₆Sn₅ layer was revealed, if the Cu content was up to 1 wt.%. With the aid of microstructure evolution, quantitative analysis, and elemental distribution by x-ray color mapping, the presence of the Ni-Sn-P phase and P-rich layer was evidenced.     

Methodology for studying the impact of intrinsic stress on thereliability of the electroless Ni UBM structure

A methodology for evaluating the reliability and the impact of intrinsic stresses on the electroless Ni under bump metallurgy (UBM) structure is presented. The first part of this work will address the testing methodology, which uses a pressure sensing device to determine the intrinsic stress in Ni due to the plating process. An optical method is used to capture deformation in the sensing device due to the Ni plating process. A finite element model is then used to calculate the intrinsic stress in the Ni film using the deformation output from the optical measurements. The second part of this work will address a predictive model used to determine the reliability of applying intrinsic stress values to a low cost electroless Ni UBM structure during the bump formation and solder reflow process. The combined work of the testing and predictive methodology provides a more effective and accurate method of predicting the Ni UBM reliability     

High rate magnetron RIE of thick polyimide films for advanced computer packaging applications

High performance (high speed and high wiring density) computer packaging can be obtained by applying thin film technology to the multichip interconnection structure. The thickness of the layers, as determined by the electrical requirements, necessitates the use of a via-fill process in conjunction with straight-wall openings in the dielectric layers. The packaging performance and wiring density is improved through reduced via areal dimensions (increased number of lines per layer), through elimination of stepcoverage limitations, and through better planarity thus increasing the number of signal and power layers. The MCNC split cathode magnetron was found to be the best RIE system for obtaining high rate low pressure oxygen RIE of polyimide films. The polyimide etch process was studied, characterized and optimized for the anisotropic residue free etch of 4 μm to 12 μm thick polyimide films. The etched wafers were then processed through the subsequent via filling step and reproducible planar via-filling was achieved with an electroless Ni plating process.     

<Emphasis Type="Italic">In Situ</Emphasis> Stress Measurements During GaN Growth on Ion-Implanted AlN/Si Substrates

In situ wafer curvature measurements were used in combination with postgrowth structural characterization to study the evolution of film stress and microstructure in GaN layers grown by metalorganic chemical vapor deposition on N⁺ ion-implanted AlN/Si (111) substrates. The results were compared with growth on identical unimplanted substrates. In situ stress measurements revealed that, for the unimplanted sample, the GaN initiated growth under compressive stress of −1.41 GPa which arose due to lattice mismatch with the AlN buffer layer. In contrast, GaN growth on the ion-implanted sample began at lower compressive stress of −0.84 GPa, suggesting a reduction in epitaxial stress. In both cases, the compressive growth stress was fully relaxed after ~0.7 μm and minimal tensile stress was generated during growth. During post-growth cooling, tensile stress was introduced in the GaN layer of both samples due to thermal expansion mismatch. Post-growth optical microscopy characterization, however, demonstrated that the ion-implanted sample had lower density of channeling cracks compared with the unimplanted sample. Cross-sectional transmission electron microscopy images of the sample grown on ion-implanted Si with no post-implantation nitrogen annealing revealed the formation of horizontal cracks in the implanted region beneath the AlN buffer layer. The weakened layer acts to decouple the GaN film from the Si substrate and thereby reduces the density of channeling cracks in the film after growth.     

Al/Ni薄膜自蔓延反应连接温度场模拟及分析

自蔓延反应能在极短时间内产生足够集中的热量熔化钎料实现材料的连接,具有连接效率高、对连接母材热影响小等特点,从而在材料连接和电子封装领域有着广泛的应用前景。针对Cu/Cu和Cu/Si两种互连结构,建立Ai/Ni薄膜自蔓延反应的连接温度场有限元模型,分析不同钎料厚度、预热条件等参数以及不同连接材料对自蔓延反应连接温度场的影响规律。