Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $hbox{La}_{2}hbox{O}_{3}/hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High- $kappa$ Dielectrics and Si Channel

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.     

Improved High-Temperature Leakage in High-Density MIM Capacitors by Using a TiLaO Dielectric and an Ir Electrode

We have fabricated high-kappa TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 times 10^-7 A/cm² was obtained at 125degC for 24-fF/mum2 density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.     

Good High-Temperature Stability of TiN/ Al2O3/WN/TiN Capacitors

For the first time, good thermal stability up to an annealing temperature of 1000degC has been demonstrated for a new TiN/Al₂O₃/WN/TiN capacitor structure. Good electrical performance has been achieved for the proposed layer structure, including a high dielectric constant of ~ 10, low leakage current of 1.2times10^-7 A/cm² at 1 V, and excellent reliability. A thin WN layer was incorporated into the metal-insulator-metal capacitor between the bottom TiN electrode and the Al₂O₃ dielectric suppressing of interfacial-layer formation at Al₂ O₃/TiN interfaces and resulting in a smoother Al₂O₃/TiN interface. This new layer structure is very attractive for deep-trench capacitor applications in DRAM technologies beyond 50 nm.     

High-Work-Function Ir/HfLaO ${rm p}$-MOSFETs Using Low-Temperature-Processed Shallow Junction

We report a high effective work function (Phi_m-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO₂-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phi_m-eff of 5.3 eV, low V_t of +0.05 V, high mobility of 90 cm²/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

Performance Improvement of $hbox{Sm}_{2}hbox{O}_{3}$ MIM Capacitors by Using Plasma Treatment After Dielectric Formation

In this letter, we investigate the dependence of the performance of metal-insulator-metal (MIM) capacitors with Sm₂O₃ dielectric on plasma treatment (PT) performed before Sm₂O₃ deposition, after Sm₂O₃ deposition, or both before and after Sm₂O₃ deposition. By performing PT in N₂ ambient (PTN) after Sm₂O₃ dielectric formation, the effective quadratic voltage coefficient of capacitance (VCC) can be reduced from 498 to 234 ppm/V² and the effective linear VCC can be reduced from 742.3 to 172 ppm/V for MIM capacitor with Sm₂O₃ dielectric having a capacitance density of ~ 7.5 fF/mum². The leakage current density at +3.3 V can be reduced from 3.44 10^-7 to 1.60 times 10^-8 A/cm² by performing PTN in both before and after Sm₂O₃ deposition. PTN after dielectric formation is an effective way to improve the performance of high-kappa dielectric MIM capacitors for RF and analog/mixed signal IC applications.     

Novel Integration of Metal–Insulator–Metal (MIM) Capacitors Comprising Perovskite-type Dielectric and Cu Bottom Electrode on Low-Temperature Packaging Substrates

In this letter, a novel integration scheme, for metal-insulator-metal capacitors comprising perovskite-type dielectrics and Cu-based bottom electrodes, has been demonstrated on low-temperature FR4 packaging substrates. Cu oxidation during dielectric deposition and postannealing is completely avoided by a dielectric-first process flow with Ti as oxygen-getter. By using evaporated barium strontium titanate as capacitor dielectric, a maximum capacitance density (~1250 nF/cm² at 100 kHz) and moderate leakage current (< 4 times 10^-5 A/cm² at 2 V) have been achieved with rapid thermal annealing at 700degC. Higher temperature leads to dielectric degradation. Combined with advanced deposition techniques, this integration scheme enables realization of high-performance embedded capacitors that can be integrated with printed circuit board technology.     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

High-Performance MIM Capacitors Using HfLaO-Based Dielectrics

Metal-insulator-metal (MIM) capacitors fabricated with (8%) La-doped HfO₂ single layer as well as HfLaO/ LaAlO₃/HfLaO multilayer dielectric stack are demonstrated. While the La-doped HfO₂ single layer is crystallized at 420^°C annealing, HfLaO/LaAlO₃/HfLaO multilayer dielectric stack remains amorphous. A high dielectric-constant value of 38 can be obtained when 8% La-doped HfO₂ is crystallized into cubiclike structure. However, it is observed that the linearity of MIM capacitor is degraded upon crystallization. The multilayer film has lower average dielectric constant but shows low quadratic voltage linearity of less than 1000 ppm/V² up to a capacitance density of 9 fF/?m² . It is observed that the HfLaO single-layer MIM is suitable for the applications with requirements of high capacitance density and robust reliability, while the multilayer MIM is suitable for a precision circuit.     

Increasing the current density of dielectric-base transistors withan MgO emitter-base barrier

We measured the current-voltage characteristics of YBa₂Cu₃O_7-x/oxide/n-SrTiO₃ diodes using NdGaO₃, LaAlO₃, CeO₂, and MgO as the oxide. MgO films had the highest current density. We then fabricated dielectric-base transistors with a YBa₂Cu₃ O_7-x(YBCO) emitter/collector on a SrTiO₃ dielectric base with an MgO barrier. The transistors had both voltage and current gains exceeding unity at 4.2 K. The emitter current density was about 4×10³ A/cm² at a collector-emitter voltage of 10 V and base-emitter voltage 10 V; this is 2 to 3 orders of magnitude larger than that of transistors with NdGaO₃ emitter-base barrier. We obtained a transconductance of around 0.4 mS at a collector-emitter voltage of 10 V for a device with a 6-μm-diameter emitter     

Transparent Thin-Film Transistors Using ZnMgO as Dielectrics and Channel

An enhancement-mode ZnMgO transparent thin-film transistor (TFT) is fabricated, in which cubic-phase ZnMgO (C-ZnMgO) is used as gate insulator and hexagonal-phase ZnMgO (H-ZnMgO) is used as channel. The multilayers of C-ZnMgO and H-ZnMgO are grown on patterned indium-tin-oxide-coated glass in successive fashion at low temperature. Capacitor-voltage characteristics measured across the gate show that the H-ZnMgO channel is n-type. The C-ZnMgO isolating layer demonstrates low leakage current characteristics, i.e., 4 times 10^-7 A/cm², at a bias of 10 V. The transparent TFTs display a typical channel mobility of 1.5 cm² V^-1 s^-1 and an on/off ratio of 10⁴.     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

High-Temperature Stable HfLaON p-MOSFETs With High-Work-Function Ir3Si Gate

We report a novel 1000 degC stable HfLaON p-MOSFET with Ir₃ Si gate. Low leakage current of 1.8times10^-5 A/cm² at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm²/Vmiddots are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degC rapid thermal annealing is fully compatible to current very large scale integration fabrication lines     

Surface Leakage in GaN/InGaN Double Heterojunction Bipolar Transistors

We report a study on the surface-leakage current in GaN/InGaN double heterojunction bipolar transistors (DHBTs) that are grown on a sapphire substrate. Surface-leakage-current densities on an unpassivated DHBT are 9.6 times 10^-5 - 5.8 times 10^-4 A/cm for JC = 0.5-50 A/cm². A fabricated n-p-n GaN/InGaN DHBT shows the common-emitter dc current gain of 42, the collector-current density of 5.2 kA/cm², and the common-emitter breakdown voltage (BV_CEO) of 75 V.     

Low-threshold room-temperature operation of injectorless quantum-cascade lasers: influence of doping density

The influence of the doping density in the active sections of InP-based injectorless quantum cascade lasers, emitting at 6.8 mum, is investigated. The doping sheet density is varied in the range 2.5-8.6times10¹⁰ cm^-2. Lasing is observed in the whole range, with a threshold current density as low as 1.2 kA/cm² at 300 K for the smallest doping sheet density of 2.5times10 ¹⁰ cm^-2. Further improvement has been made by additionally increasing the number of periods in the active region from 40 to 60. With the same doping level of 2.5times10¹⁰ cm^-2 record low threshold current densities of 0.73 kA/cm² at 300 K were achieved