Low-power fault-tolerant interconnect method based on LCDMA and duplication

High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.     

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.     

基于CPLD的容错存储器的设计实现

分析了存储器产生错误的原因 ,提出了提高其可靠性的有效途径。结合航天计算机可靠性增长计划 ,给出了一套利用纠检错芯片对其进行容错的方案 ,并给出了通过 CPL D器件实现的仿真结果。最后对容错存储器的可靠性进行了分析。     

Soft errors issues in low-power caches

As technology scales, reducing leakage power and improving reliability of data stored in memory cells is both important and challenging. While lower threshold voltages increase leakage, lower supply voltages and smaller nodal capacitances reduce energy consumption but increase soft errors rates. In this work, we present a comprehensive study of soft error rates on low-power cache design. First, we study the effect of circuit level techniques, used to reduce the leakage energy consumption, on soft error rates. Our results using custom designs show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. We also validate the effects of voltage scaling on soft error rate by performing accelerated tests on off-the-shelf SRAM-based chips using a neutron beam source. Next, we study the impact of cache decay and drowsy cache, which are two commonly used architectural-level leakage reduction approaches, on the cache reliability. Our results indicate that the leakage optimization techniques change the reliability of cache memory. More importantly, we demonstrate that there is a tradeoff between optimizing for leakage power and improving the immunity to soft error. We also study the impact of error correcting codes on soft error rates. Based on this study, we propose an adaptive error correcting scheme to reduce the leakage energy consumption and improve reliability.     

低电压下CMOS数字电路概率模型研究

为解决数字电路低功耗问题,电路工作电压被不断降低,导致电路逻辑器件呈现概率特性。本文提出了低电压下CMOS数字电路的错误概率模型,并完成硬件电路测试验证。本文首先详述了深亚微米（DSM）量级的门电路及模块在低电压供电条件下导致器件出错的因素,结合概率器件结构模型推导基本逻辑门概率模型,并提出了状态转移法用于完成由门级到模块级的概率分析模型;我们搭建硬件平台对CMOS逻辑芯片进行了低供电压测试,通过分析理论推导结果与实测结果,验证并完善了分析模型。实验结果表明,由状态转移法推导的电路概率模型符合电路实际性能,从而为构建低电压下数字电路概率模型提供了可靠分析模型。      

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.     

A Fault Tolerant Hierarchical Network on Chip Router Architecture

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures. In this paper, we propose an enhanced fault tolerant microarchitecture with deadlock-free routing for Hierarchical NoCs. The proposed router supplies dynamic Virtual Channel (VC) Allocation, and it employs a high-performance fault tolerant control flow, handling both transient and permanent faults in hierarchical networks without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.     

两种低功耗新型过温保护电路的设计

电源管理芯片中过温保护电路用来检测芯片的温度。当温度过高时,过温保护电路输出保护信号,使芯片停止工作,以免温度过高而损坏芯片。为了实现上述过温保护电路功能,提出了两种新型的过温保护电路,不但能够精确地检测芯片的温度,并且功耗很低。采用0．5μm N-阱CMOS工艺的方法,进行电路设计,并使用CadenceSpectre工具进行了仿真实验验证。仿真实验结果表明两种电路仅消耗3μA的电流就能够实现精确的温度检测,其具有较强的适应性,高灵敏度和高精度的特点,应用前景比较广泛。     

Adaptive fault-tolerant DVFS with dynamic online AVF prediction

Advances in silicon technology and shrinking the feature size to nanometer levels make random variations and low reliability of nano-devices the most important concern for fault-tolerant design. Design of reliable and fault-tolerant embedded processors is mostly based on developing techniques that compensate reliability shortcomings by adding hardware or software redundancy. The recently-proposed redundancy adding techniques are generally applied uniformly to all parts of a system and lead to heavy overheads and inefficiencies in terms of performance, power, and area. Efficient employment of non-uniform redundancy becomes possible when a quantitative analysis of a system behavior while encountering transient faults is provided. In this work, we present a quantitative analysis of the behavior of an embedded processor regarding transient faults and propose a new approach that accurately predicts the architecture vulnerability factor (AVF) in real-time. Another critical concern in design of new-silicon processors is power consumption issue. Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy consumption and performance of a system. Since rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFS techniques are recently shown to have compromising effects on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault rate could considerably degrade the system reliability. Here, by exploiting the proposed online AVF prediction methodology and based on analytic derivation, we propose a reliability-aware adaptive dynamic voltage and frequency scaling (DVFS) approach in case study of Multi-Processor System on Chip (MPSoC) with Multiple Clock Domain (MCD) pipeline architectures in which the frequency and voltage are scaled by simultaneously considering all three of power consumption, reliability, and performance. Comparing to the traditional methods of reliability-aware DVFS systems, the proposed reliability-aware DVFS method yields 50% better power saving at the same reliability level.     

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V _DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.     

一种自恢复容SEU锁存器的设计

随着集成电路工艺水平的不断提高、器件尺寸的不断缩小以及电源的不断降低,传统的锁存器越发容易受到由辐射效应引起的软错误影响。为了增强锁存器的可靠性,提出了一种适用于低功耗电路的自恢复SEU加固锁存器。该锁存器由传输门、反馈冗余单元和保护门C单元构成。反馈冗余单元由六个内部节点构成,每个节点均由一个NMOS管和一个PMOS管驱动,从而构成自恢复容SEU的结构。在45 nm工艺下,使用Hspice仿真工具进行仿真,结果表明,与现有的加固方案FERST[1]结构相比,在具备相同面积开销和单粒子翻转容忍能力的情况下,提出的锁存器不仅适用于时钟门控电路,而且节省了61.38%的功耗-延迟积开销。     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

用于低开销容错设计的存储部件可靠性评估研究

低开销容错技术是当前软错误研究领域的热点。为了对微处理器进行低开销容错保护,首先就需要对微处理器可靠性(即体系结构弱点因子AVF (Architectural Vulnerability Factor))进行准确评估。然而,现有的AVF评估工具的精确性和适用范围都受到不同程度的限制。该文以微处理器上的核心部件(即存储部件)作为研究对象,对AVF评估方法进行改进,提出了一种访存操作分析和指令分析相结合的AVF评估策略HAES (Hybrid AVF Evaluation Strategy)。该文将HAES融入到通用的模拟器中,实现了更精确和更通用的AVF评估框架。实验结果表明相比其它AVF评估工具,利用该文提出的评估框架得到的AVF平均降低22.6%。基于该评估框架计算得到的AVF更加精确地反映了不同应用程序运行时存储部件的可靠性,对设计人员对微处理器进行低开销的容错设计具有重要指导意义。     

Cell-plate line connecting complementary bit-line (C3)architecture for battery-operated DRAMs

In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line connecting complementary bit-line (C³) architecture, which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliability of the memory cell capacitor dielectric film, is proposed. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6-μm×3.2-μm cell size. This architecture should open the path for the future battery-backup and/or battery-operated high-density DRAMs     

Sleepy Stack Leakage Reduction

Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit structure which we call "sleepy stack". Unlike many other previous approaches, sleepy stack can retain logic state during sleep mode while achieving ultra-low leakage power consumption. We apply the sleepy stack to generic logic circuits. Although the sleepy stack incurs some delay and area overhead, the sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem     

Fault Tolerant Single Error Correction Encoders

Soft errors are an important issue for circuit reliability. To mitigate their effects on the system functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are used to protect circuits. Single Error Correction (SEC) codes are commonly used in memories and can effectively remove errors as long as there is only one error per word. Soft errors however may also affect the circuits that implement the Error Correcting Codes: the encoder and the decoder. In this paper, the protection against soft errors in the ECC encoder is studied and an efficient fault tolerant implementation is proposed.     

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification

Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated circuits (IC) that are becoming a major threat in modern sub 45nm ICs. Therefore, researchers have developed many techniques to mitigate the soft errors and some of them utilize the built in error detection schemes of low-power asynchronous null conventional logic (NCL). However, it requires extensive simulations and emulations for careful and complete analysis of the design, which can be costly, time consuming and cannot encompass all the possible input conditions. In this paper, we propose a framework to improve the soft error tolerant asynchronous pipelines by identifying and formally analyzing the vulnerable paths using the nuXmv model checker. The proposed framework translates the design behavior and specification into a state-space model and the potential vulnerabilities against soft errors in the pipeline as linear temporal logical (LTL) properties. These formally specified properties are then verified on the state-space model and in case of failure counterexamples are obtained. These counterexamples can then be further analyzed to obtain the soft error propagation paths and thus give insights about soft error tolerant approaches to the designers. For illustration, this work provides an analysis and comparison of three state-of-the-art asynchronous pipelines. Formal model and analysis of all the pipelines show that the soft error hardened pipeline is comparatively superior against soft errors but at the expense of almost two times area overhead.