Thermal sensor allocation for 3DICs using three dimensional thermal sensors

Stacking active layers leads to increased power density and overall higher temperatures in a three dimensional integrated circuit (3DIC). Thermal sensors are therefore crucial for run-time thermal management of 3DICs. A thermal sensor allocation method customized for 3DICs that utilizes ring oscillator based 3D sensors is introduced in this paper. A new 3D thermal map modeling method that facilitates efficient and very fast analyses is embodied in this thermal sensor distribution algorithm. Our results indicate that for a 4-layer stacked 3DIC, consisting of two layers of quad-core processors and one layer of L2 cache and one layer of main memory, less than 3.58% in maximum sensor reading error can be accomplished with a 53× speedup in the thermal evaluation time and thermal sensor distribution algorithm implementation.     

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

State-of-the-art devices in the consumer electronics market are relying more and more on Multi-Processor Systems-On-Chip (MPSoCs) as an efficient solution to meet their multiple design constrains, such as low cost, low power consumption, high performance and short time-to-market. In fact, as technology scales down, logic density and power density increase, generating hot spots that seriously affect the MPSoC performance and can physically damage the final system behavior. Moreover, forthcoming three-dimensional (3D) MPSoCs can achieve higher system integration density, but the aforementioned thermal problems are seriously aggravated. Thus, new thermal exploration tools are needed to study the temperature variation effects inside 3D MPSoCs. In this paper, we present a novel approach for fast transient thermal modeling and analysis of 3D MPSoCs with active (liquid) cooling solutions, while capturing the hardware-software interaction. In order to preserve both accuracy and speed, we propose a close-loop framework that combines the use of Field Programmable Gate Arrays (FPGAs) to emulate the hardware components of 2D/3D MPSoC platforms with a highly optimized thermal simulator, which uses an RC-based linear thermal model to analyze the liquid flow. The proposed framework offers speed-ups of more than three orders of magnitude when compared to cycle-accurate 3D MPSoC thermal simulators. Thus, this approach enables MPSoC designers to validate different hardware- and software-based 3D thermal management policies in real-time, and while running real-life applications, including liquid cooling injection control.     

Thermal compact modeling approach of droplet microreactor based Lab-on-a-Chip devices

The paper presents a novel compact model which enables the thermal analysis of microchannels consisting of continuously moving microdroplets with biologically active content inside. The compact model utilizes the switched capacitor approach to describe the convective heat transfer and as a behavioral model, it can be easily integrated into an IC-MEMS design flow. With this novel approach the temperature profile of the channel can be calculated in minutes compared to conventional numerical techniques that requires days or weeks. The model was validated by a standard CFD solver and a good match was achieved.     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

三维人脸建模技术分析及应用

三维人脸建模是计算机视觉和计算机图形学领域中一个研究热点,笔者首先分析了三维人脸建模技术背景意义和研究现状;其次论证了各种三维人脸建模技术的优缺点;最后对三维人脸建模技术的应用领域进行了详细介绍并进一步展望了今后三维人脸建模方向。     

Thermal modeling and analysis of 3D multi-processor chips

As 3D chip multi-processors (3D-CMPs) become the main trend in processor development, various thermal management strategies have been recently proposed to optimize system performance while controlling the temperature of the system to stay below a threshold. These thermal-aware policies require the envision of high-level models that capture the complex thermal behavior of (nano)structures that build the 3D stack. Moreover, the floorplanning of the chip strongly determines the thermal profile of the system and a quick exploration of the design space is required to minimize the damage of the thermal effects.This paper proposes a complete thermal model for 3D-CMPs with building nano-structures. The proposed thermal model is then used to characterize the thermal behavior of the Niagara system and expose the strong influence of the chip floorplanning in the thermal profile.     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

基于虚拟现实的三维建模技术的研究

随着VR（虚拟现实技术）的快速发展,三维建模技术在其中发挥着重要的作用,是虚拟现实技术的核心。本文研究探讨了VR技术和三维建模技术,以及建模软件3D MAX,还对VRML语言进行了分析论述。     

Fast and accurate thermal modeling and simulation of manycore processors and workloads

Today's microprocessors require careful analysis of their thermal behavior both at design time as well as at runtime. However, accurate prediction of thermal behavior is possible only through simulations due to the complexity and the high dynamicity of their operation. Unfortunately, accurate simulations of such complex systems are computationally intensive, therefore time consuming, while on the other hand, simplified models often cause mispredictions leading to overdesign and lowered performance. In our work, we propose a new discrete-time method of assessment of the run-time temperature of a processor based on an approximation of its instructions-per-cycle (IPC) by a finite Fourier series expansion. Our method is AC-based, and shows significant increase of accuracy in comparison to well-known DC (average)-based models. Furthermore, we provide a new Dynamic Voltage and Frequency Scaling (DVFS) model based on our estimations.     

Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs

In this paper, we investigate the co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. The architecture is a 16 core, ×86 multicore die stacked with a second die hosting an L2 SRAM cache. First, a multicore ×86 compatible cycle-level microarchitecture simulator was constructed and integrated with physical power models. The simulator executes benchmark programs to create power traces that drive thermal analysis. Second, the thermal characteristics under liquid cooling were investigated using a compact thermal model. Four alternative packaging organizations were studied and compared. The greatest overall temperature reduction under a given pumping power is achieved, with two tiers and two pin fin enhanced microgaps, with the high power dissipation tier on the top. Third, an optimization of the pin fin parameters including the diameter, height, and longitudinal and transversal spacing was performed. This optimization is shown to achieve significant improvement in energy/instruction, and significant reductions in leakage power.     

PCB制造信息提取与快速3D建模

从PCB格式文件中提取制造信息,通过VBA开发EXCEL实现对制造信息的自动筛选、归类和数据库存储。利用UG的知识熔接功能,建立制造信息转换通道,将处理后的制造信息导入UG,在UG中进行自动快速3D建模。利用UG和ANSYS的接口,可将模型导入ANSYS进行有限元分析。     

Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling

A computationally-efficient 3D phase-field model for simulating grain growth in through silicon vias (TSVs) is presented. The model is capable of simulating grain growth in the cylindrical shape of a TSV. The results generated from the phase-field simulations are used in a finite element model with anisotropic elastic and isotropic plastic effects to investigate the large statistical distribution of Cu pumping (i.e. the irreversible thermal expansion of TSV) experimentally seen. The model thus allows to correlate the macroscopic plastic deformation with the grain size and grain orientations.     

Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system

In this work different VHDL-based fault injection techniques (simulator commands, saboteurs and mutants) have been compared and applied in the validation of a fault-tolerant system. Some extensions and implementation designs of these techniques have been introduced. As a complement of these injection techniques, a wide set of fault models (including several non-usual models) have been implemented. We have injected both transient and permanent faults on the system model, using two different workloads, with the help of a fault injection tool that we have developed. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.     

一种交互编辑与自动生成的三维地形综合构建方法与实现

随着视景仿真技术的发展,三维地形建模作为其重要内容也越来越成为人们关注的热点。目前三维地形建模的主要方法有交互编辑和自动生成两种,然而交互编辑法效率低且对专业知识要求高,自动生成法控制作用弱、随机性强。针对这些问题,本文提出一种建模方法,对交互编辑和自动生成进行综合,既能提供给用户对建模过程的控制又保证了建模的效率。基于这一方法实现了一个地形编辑系统,验证了方法的可行性和有效性。     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

SiP协调设计和PI解析(3)

SiP协调设计和PI解析:(1)封装和热设计,(2)芯片的三维安装.     

Image-based rendering and 3D modeling: A complete framework

Multi-viewpoint synthesis of video data is a key technology for the integration of video and 3D graphics, as necessary for telepresence and augmented-reality applications. This paper describes a number of important techniques which can be employed to accomplish that goal. The techniques presented are based on the analysis of 2D images acquired by two or more cameras. To determine depth information of single objects present in the scene, it is necessary to perform segmentation and disparity estimation. It is shown, how these analysis tools can benefit from each other. For viewpoint synthesis, techniques with different levels of tradeoff between complexity and degrees of freedom are presented. The first approach is disparity-controlled view interpolation, which is capable of generating intermediate views along the interocular axis between two adjacent cameras. The second is the recently introduced incomplete 3D technique, which in a first step extracts the texture of the visible surface of a video object acquired with multiple cameras, and then performs disparity-compensated projection from the surface onto a view plane. In the third and most complex approach, a 3D model of the object is generated, which can be represented by a 3D wire grid. For synthesis, this model can be rotated to arbitrary orientations, and original texture is mapped onto the surface to obtain an arbitrary view of the processed object. The result of this rendering procedure is a virtual image with very natural appearance.     

机械三维建模及3D打印课程教学模式研究

三维建模软件在机械行业中越来越受到重视,相关软件的教学也成为机械大类专业的核心课程。以CREO 3.0为例,探讨了机械类三维建模课程的教学内容等到,并且进一步说明了作者在教学实践中的模式,在课程体系、教学资源建设、教学手段等方面都提出了新的理念和做法。