Three-Dimensional Closed-Form Model for Potential Barrier in Undoped FinFETs Resulting in Analytical Equations for $V_{T}$ and Subthreshold Slope

An analytical approach for modeling the electrostatic potential in nanoscale undoped FinFETs is derived. This method uses a 2-D solution for this potential within a double-gate FET and takes into account the top gate electrode as the third dimension by applying the conformal mapping technique. Herewith, an analytical closed-form model for the height of the potential barrier below threshold is defined which includes 3-D effects. From that, models for subthreshold slope and threshold voltage of nanoscale triple-gate FETs are derived. The results are in good agreement with numerical device simulation results and measurements for channel lengths down to 20 nm.      

Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation

A threshold voltage model for mesa-isolated fully depleted silicon-on-insulator (FDSOI) MOSFETs, based on the analytical solution of three-dimensional (3-D) Poisson's equation is presented for the first time in this paper. The separation of variables technique is used to solve the 3-D Poisson's equation analytically with appropriate boundary conditions. Simple and accurate analytical expressions for the threshold voltage of the front and the back gate are derived. The model is able to predict short channel as well as narrow width effects in mesa-isolated FDSOI MOSFETs. The model is validated by comparing with the experimental results as well as with the numerical results available in the literature.     

Two-dimensional numerical analysis of the narrow gate effect in MOSFET

Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.     

An analytical grain-barrier height model and its characterizationfor intrinsic poly-Si thin-film transistor

An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFTs) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for a wide gate voltage range     

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

A 2-D analytical solution for SCEs in DG MOSFETs

A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.     

An analytical solution to a double-gate MOSFET with undoped body

A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS     

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI.     

Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation

The potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field-effect transistors with doped and undoped channels. The accuracy of the model has been verified by the data from 3-D numerical device simulator. The variation of subthreshold slope and threshold voltage with device geometry and doping concentration in the channel has been studied.     

A 2-D analytic model for the threshold-voltage of fully depletedshort gate-length Si-SOI MESFETs

A two-zone Green's function solution method is proposed to analytically model the potential distribution in the silicon film of fully depleted SOI MESFETs, in which the exact solution of 2-D Poisson's equation is obtained by using the appropriate boundary conditions. From the derived analytic 2-D potential distribution, the bottom potential in the active silicon film is used to analyze the drain-induced barrier lowering effect and the threshold voltage is defined in terms of minimum channel potential barrier. The results of the developed analytic threshold-voltage model are compared with those of 2-D numerical simulation, and good agreements are obtained for the gate length down to 0.1 μm with wide ranges of structure parameters and bias conditions     

Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs-InGaAs symmetric double-gate HEMT

This paper presents an approximate solution of a 2-D Poisson’s equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results.     

Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs

We have developed analytical physically based models for the threshold voltage [including the drain-induced barrier lowering (DIBL) effect] and the subthreshold swing of undoped symmetrical double-gate (DG) MOSFETs. The models are derived from an analytical solution of the 2-D Poisson equation in which the electron concentration was included. The models for DIBL, subthreshold swing, and threshold voltage roll-off have been verified by comparison with 2-D numerical simulations for different values of channel length, channel thickness, and drain-source voltage; very good agreement with the numerical simulations has been observed     

A subthreshold model of the narrow-gate effect in MOSFET's

The subthreshold softening characteristic of MOSFET's due to the narrow-gate effect has been investigated based on the two-dimensional (2-D) numerical solution of the Poisson equation and device physics. Numerical results taken on stepped-oxide MOSFET's with different gate widths show that a narrower gate width device tends to give higher cut-off voltage. Two parameters account for the softening of the subthreshold characteristics: the subthreshold slope of the drain conductance-gate voltage characteristic and the effective channel width. Both parameters can be extracted easily from the theoretical 2-D computed or experimental drain conductance-gate voltage characteristics. A two-parameter analytical approximation formula for narrow-gate MOSFETs operating in the subthreshold range is thus proposed and tested against exact 2-D numerical results, showing good accuracy. This model is the first one ever reported.     

Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

A simple and accurate analytical model for the threshold voltage of AlGaN/GaN high electron mobility transistor (HEMT) is developed by solving three-dimensional (3-D) Poisson equation to investigate the short channel effects (SCEs) and the narrow width effects present simultaneously in a small geometry device. It has been demonstrated that the proposed model correctly predicts the potential and electric field distribution along the channel. In the proposed model, the effect of important parameters such as the thickness of the barrier layer and its doping on the threshold voltage has also been included. The model is, further, extended to find an expression for the threshold voltage in the sub-micrometer regime. The accuracy of the proposed analytical model is verified by comparing the model results with 3-D device simulations for different gate lengths and widths.     

Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile

A novel approximation of 2-D potential function perpendicular to the channel for fully depleted (FD) silicon-on-insulator (SOI) MOSFETs on films with vertical Gaussian profile is proposed in the paper, then an analytical threshold voltage model is derived. The model agrees well with the MEDICI numerical simulation results. It represents a feasible way to find the threshold voltage and gives some reference points in developing new 2-D models for nonuniform FD-SOI devices.     

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V_T and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, σV_T , of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that σV_T, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V_T-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V_T-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 μm and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles     

Two-dimensional self-consistent simulation of a triangular p-channel SOI nano-flash memory device

This paper presents the simulation of an SOI nano-flash memory device. The device is composed of a triangular quantum wire channel p-MOSFET with a self-aligned nano-floating gate embedded in the gate oxide. The simulation is carried out by combining TSUPREM-4 and a two-dimensional (2-D) self-consistent solution of the Poisson and Schrodinger equations. The fabrication process as well as quantum physics are taken into account. Hole distribution in the inversion layer of the triangular channel section is calculated in terms of wave functions and energy subbands. The threshold voltage shift between the programming and erasing of the device is investigated. In this paper, we show that the channel shape plays a crucial role in the programming voltage and the threshold voltage shift. Based on the fact that the holes are confined mainly at the top of the triangular channel section, we explain why our triangular channel device can be operated at relatively low programming voltage despite of a thick gate oxide and tunnel oxide. The threshold voltage shift in the triangular channel device is compared with that in a rectangular channel device. The result shows that the triangular channel device exhibits the larger threshold voltage shift.     

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results.