Particle on Bump (POB) technique for ultra-fine pitch chip on glass (COG) applications by conductive particles and adhesives

Chip on glass (COG) technology is widely used in liquid crystal display (LCD) modules for connecting driver ICs to the displays especially for middle and small size panels. The most common COG technology currently used in display applications is based on anisotropic conductive films (ACF). As the increasing demand in higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. With the reduction of bump pitch, the current ACF based COG technology is confronted with two issues: one is the increase of the chances of open circuit; the other is the increase of the chances of forming shorts. A new approach for ultra-fine pitch chip on glass (COG) bonding, named ”Particle on Bump (POB)”, is proposed in this paper. In this technique, conductive particles are planted on the top surface of bumps of a driver IC through Au–Sn intermetallic connection. The driver IC is then assembled on the glass substrate of a LCD panel with an insulated adhesive by thermal press. The new method ensures that electrical connections are established only between bumps and corresponding pads. The Au–Sn reflow process for particle planting and corresponding COG bonding process were investigated in detail. The results showed that reliable connections were formed between particles and bumps through an Au–Sn intermetallic layer and final COG interconnections thus formed performed well in reliability tests. It is concluded that the POB technique overcomes the shortcomings of current ACF technique and has good potential to provide a viable ultra-fine pitch flip chip on glass solution for display applications.     

集成电路封装中的引线键合技术

在回顾现有的引线键合技术之后,文章主要探讨了集成电路封装中引线键合技术的发展趋势。球形焊接工艺比楔形焊接工艺具有更多的优势,因而获得了广泛使用。传统的前向拱丝越来越难以满足目前封装的高密度要求,反向拱丝能满足非常低的弧高的要求。前向拱丝和反向拱丝工艺相结合,能适应复杂的多排引线键合和多芯片封装结构的要求。不断发展的引线键合技术使得引线键合工艺能继续满足封装日益发展的要求,为封装继续提供低成本解决方案。     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

玻璃板上芯片封装关键装备研制与工艺开发

本项目采用高新技术和先进的实用技术,开发热压头机构、ACF供给机构、ACF剪切和剥离机构、各种工作平台、IC供给机构、IC精密定位等机械系统。运用现代设计理论和方法,开发高定位精度的玻璃板上芯片封装(COG)工艺过程所涉及的各种运动学模型、动力学模型、控制模型及其相应的机械结构。通过计算机控制系统、伺服驱动系统、图像处理系统、温度控制系统和压力控制系统等实现高稳定性和准确工艺要求下的ACF、IC芯片和玻璃基板的粘贴动作的形成和协调等问题。使开发的设备满足COG工艺过程的需求和动作的精确和稳定。     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

应用于平板显示器封装的ACF新进展

随着平板显示器大型化、薄型化、高分辨率的发展趋势,对平板显示器封装技术提出了更高的要求.ACF符合电子线路封装精细化、集成化的发展要求,目前已广泛应用于平板显示器(例如LCD)的封装领域.综述了ACF应用于平板显示器封装的主要形式如TCP、COF、COG,分析了各种不同封装形式对ACF提出的不同性能要求,以及为了满足这些要求对ACF中导电粒子的大小、含量、硬度以及ACF中使用树脂的种类等方面进行结构性能改进的最新进展.     

平板显示器中应用ACF的驱动IC封装技术

文章叙述了ACF（Anisotropic Conductive Film,各向异性导电膜）与驱动IC（Integrated Circuit,集成电路）芯片封装的历史,并强调了驱动IC封装在实现显示器微型化、高分辨率、低成本及高显示质量等方面的重要性。文章还对微细间距COF（Chip on Flex）连接用ACF的材料设计进行了介绍。文章指出低温固化ACF可以改善LCD（Liquid Crystal Display,液晶显示屏）模块的生产效率,降低大型LCD模块表面的热应力;同时指出COG（Chip on Glass）连接后LCD面板的翘曲变形引起LCD模块漏光事故。ACF焊接温度的降低可以有效减少翘曲变形,避免在应用COG封装大型LCD模块的驱动IC时所产生漏光。     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Recent fluid–structure interaction modeling challenges in IC encapsulation – A review

The rapid development of computing software has facilitated multifarious research in integrated circuit (IC) packaging. Complicated and complex processes can be visualized via simulation modeling with this software. The applications of aided software enhance the fundamental physicochemical understanding and visualization of the IC encapsulation process. In this article, fluid–structure interaction (FSI) during IC encapsulation through computer-aided simulation is reviewed based on the amount of substantial work conducted from the past decades to the present. FSI phenomena in various IC encapsulations, such as wire sweep, paddle shift, lead frame deformation, IC chip, and through-silicon via (TSV) deformation, is considered in the review. The significance and challenges of FSI analysis are also highlighted in this article.     

Numerical study on the bonding tool position, tip profile and planarity angle influences on TAB/ILB interconnection reliability

Tape automated bonding (TAB) is a widely used interconnection technology for high-pincount and fine-pitch IC packaging. In this study, a three-dimensional computational model was developed for analyzing TAB inner lead bonding (ILB) process. This experimental study on the thermomechanical properties of copper leads was achieved using high precision micro-force tensile tests. A stress–stain relation between the copper lead and different temperature ranges was successfully implemented into the finite element model to study large plastic deformation in ILB formation. The resulting ILB lead profile and bump sinking values obtained from the simulations agreed well with the experimental observations from actual manufacturing data with the same bonding parameters. The tool position and lead length effects are analyzed to study the residual stress distribution after ILB. A 10-lead model was developed to study how the tool tip profile and planarity ‘angle affect the co-planarity between the bonding tool and the stage. The numerical results show that the permissible tool profile variance should not exceed 1.25 μm and the acceptable planarity angle is 0.005° to achieve the minimum bump deformation requirement.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

面板显示驱动电路的失效分析及对策

文章主要对集成电路失效问题进行分析,列举出了容易引起集成电路失效的原因:压焊劈刀选型不当,生产过程中造成芯片表面沾污,芯片表面内压焊点铝层与底层硅化合物结合不牢,选用压焊参数不当,环氧塑封料的特性不佳,存储环境恶劣导致成品电路吸潮等,并逐一进行了分析。同时,还简要的对环氧塑封料特性:耐热性、耐腐蚀性、热膨胀系数、电气特性、耐湿性、结合力方面引起集成的电路失效进行了进一步的分析,提出了预防因产品吸潮而引起塑封体与芯片表面产生分层造成集成电路失效的方法。     

电子封装技术的最新进展

现今集成电路的特征线宽即将进入亚0.1nm时代,根据量子效应这将是半导体集成的极限尺寸,电子产品小型化将更有赖于封装技术的进步.概括总结了SiP三维封装、液晶面板用树脂芯凸点COG封装、低温焊接等技术的最新进展.并对SiP三维封装技术中封装叠层FFCSP技术进行了着重的阐述.指出随着低温焊接、连接部树脂补强以及与Si热膨胀系数相近基板的出现,电子封装构造的精细化才能成为可能,为各种高密度封装、三维封装打下坚实基础.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame.The gold wire bonding process has been widely used in LED packaging industry currently.However,due to the high cost of gold wire,copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving.In this paper,the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation.This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Characteristic study of anisotropic-conductive film for chip-on-film packaging

Chip-on-film (COF) is a new technology after tape-automated bonding (TAB) and chip-on-glass (COG) in the interconnection of liquid crystal module (LCM). The thickness of the film, which is more flexible than TAB, can be as thin as 44 μm. It has pre-test capability, while COG does not have. It possesses great potential in many product fabrication applications.In this study, we used anisotropic-conductive film (ACF) as the adhesive to bind the desired IC chip and polyimide (PI) film. The electric path was formed by connecting the bump on the IC and the electrode on the PI film via the conductive particles in the ACF. In the COF bonding process experimental-design method was applied based on the parameters, such as bonding temperature, bonding pressure and bonding time. After reliability tests of (1) 60 °C/95%RH/500 h and (2) −20 to 70 °C/500 cycles, contact resistance was measured and used as the quality inspection parameter. Correlation between the contact resistance and the three parameters was established and optimal processing condition was obtained. The COF samples analyzed were fabricated accordingly. The contact resistance of the COF samples was measured at varying temperature using the four points test method. The result helped us to realize the relationship between the contact resistance and the operation temperature of the COF technology. This yielded important information for circuit design.     

Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications

Smart labels are a new generation of low cost transponders consisting of a transponder chip and a flexible type of antenna. Applying a flip chip assembly technology yields a new generation of low cost radio frequency identification (RFID) system that is a paper-thin smart label. Anisotropically conductive adhesive (ACA) is utilized to attach a flip chip onto a paper substrate to form the BiStatix RFID tag. Unlike bar codes, which are passive tags, smart labels can dynamically transmit and receive information to help identify, track and route packages remotely. The concept of flipping or inverting a silicon chip to be mounted on a paper substrate offers distinct advantages and enables achieving the cost and performance goals of this new product technology.Significant process development and reliability assessment was required to develop this smart label application. This paper discusses the process development and reliability assessment that was completed to achieve a low cost flip chip on paper assembly process. The various characteristics of ACA made it an enabling technology for this smart label application. A bare (unbumped) flip chip––without a dielectric layer and conductive polymer bumps––was aligned and placed on the paper substrate with compressive force. A thin layer of anisotropically conductive adhesive was used to attach the IC chip to the conductive ink antenna on the paper substrate. The conductive adhesive underfills and cures in only seconds. Advantages of this environmentally preferred process include the elimination of additional curing processes and reduced equipment requirements as well as the reduction of total IC packaging thickness.     

基于挠性基板的高密度IC封装技术

挠性印制电路技术迅速发展,其应用范围迅速扩大,特别是在IC封装中的应用受到人们的广泛关注。挠性印制电路在IC封装中的应用极大地推动了电子产品小型化、轻量化以及高性能化的进程。针对具体应用对象,文章分别介绍了挠性基板CSP封装、COF封装以及挠性载体叠层封装的基本工艺、关键技术、应用现状及发展趋势,充分说明了挠性印制电路和高密度布线对高密度IC封装的适用性。基于挠性基板的IC封装技术将会保持高速的发展,特别是挠性叠层型SIP封装技术具有广阔的应用前景。     

台面型焊盘的引线键合工艺研究

引线键合工艺是微电子封装的基础工艺,广泛应用于军品和民品芯片的封装。特殊结构焊盘的引线键合失效问题是键合工艺研究的重要方向。文章主要针对台面型焊盘,从热压键合、超声键合、热超声键合原理进行了分析,对台面型焊盘的工艺适应性给出了建议。使用热超声键合工艺进行台面型焊盘的引线键合需要尽可能降低超声功率,避免键合焊盘的机械损伤,并通过平衡其他各变量保证键合点的强度。侧重于热超声键合工艺的应用,分析台面型焊盘与热超声键合过程相关的失效现象,通过样件及小批量试制,对工艺参数进行了优化验证,针对故障件统计分类给出了相应的解决途径。