Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

基于混合电极两步键合工艺的阳极键合研究

提出了一种基于新型混合电极的两步键合工艺。阳极键合工艺是在自行设计的多功能键合系统中完成,分析了不同电极配置对键合时间,键合强度以及键合界面的影响,并详细分析了键合界面和键合强度。借助于新型混合电极结构,能够在15-20min内实现无气泡晶圆级阳极键合,其键合强度高于10MPa。 以上结果表明,该种键合方法有非常好的应用价值,能应用于绝大多数晶圆级MEMS封装。     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Development of a thermosonic wire-bonding process for gold wire bonding to copper pads using argon shielding

To improve the bondability and ensure the reliability of Au/Cu ball bonds of the thermosonic (TS) wire-bonding process, an argon-shielding atmosphere was applied to prevent the copper pad from oxidizing. With argon shielding in the TS wire-bonding process, 100% gold wire attached on a copper pad can be achieved at the bonding temperature of 180°C and above. The ball-shear and wire-pull forces far exceed the minimum requirements specified in the related industrial codes. In a suitable range of bonding parameters, increasing bonding parameters resulted in greater bonding strength. However, if bonding parameters exceed the suitable range, the bonding strength is deteriorated. The reliability of the high-temperature storage (HTS) test for Au/Cu ball bonds was verified in this study. The bonding strength of Au/Cu ball bonds increases slightly with prolonged storage duration because of diffusion between the gold ball and copper pad during the HTS test. As a whole, argon shielding is a successful way to ensure the Au/Cu ball bond in the TS wire-bonding process applied for packaging of chips with copper interconnects.     

Zero-level packaging using BCB adhesive bonding and glass wet-etching for W-band applications

A small size zero-level packaging method, by using wafer-level benzocyclobutene (BCB) adhesive bonding and a pyrex glass wet-etching technique, is presented. A simple process was developed to make a pyrex glass to have housing cavities and BCB sealing ring for a packaging. During a wet-etching of glass for making a cavity and pad feedthroughs, BCB was protected by 1.2 /spl mu/m-thick AZ1512 photoresist. To estimate a pyrex 7740 packaging material in W-band, a 50 W coplanar waveguide (CPW) was designed and an insertion loss (S/sub 12/) was measured. The insertion loss change of CPW lines by the fabricated package is below 0.1 dB from DC to 110 GHz.     

A mathematical model for slip phenomenon in a cavity-filling process of nanoimprint lithography

Squeeze flow theory has been used as an effective tool to clarify how and which process conditions determine cavity-filling behavior in nanoimprint lithography (NIL). Conventional squeeze flow models used in NIL research fields have assumed no-slip conditions at the solid-to-liquid boundaries, that is, at the stamp-to-polymer or polymer-to-substrate boundaries. The no-slip assumptions are often violated, however, in micrometer- to nanometer-scale fluid flow. It is therefore necessary to adopt slip or partial slip boundary conditions. In this paper, an analytical mathematical model for the cavity-filling process of NIL that takes into account slip or partial slip boundary conditions is derived using squeeze flow theory. Velocity profiles, pressure distributions, imprinting forces, and evolutions of residual thickness can be predicted using this analytical model. This paper also aims to elucidate how far the slip phenomenon is able to promote the process rate.     

Optimal design for a ball grid array wire bonding process using aneuro-genetic approach

This study presents an integrated method in which neural networks, genetic algorithms, and exponential desirability functions are used to optimize the ball grid array (BGA) wire bonding process. As widely anticipated, the BGA package will become the fastest-growing semiconductor package and push integrated circuit (IC) packaging to higher level of compactness and density. However, wire bonding in BGA is difficult owing to its high input/output (I/O) count, fine pitch wire bonds, and long wire lengths. This study addresses two fundamental issues in the semiconductor assembly facility on its quest toward a defect-free manufacturing environment. First, the problem of exploring the nonlinear multivariate relationship between parameters and responses and second, obtaining the optimum operation parameters with respect to each response in which the process should operate. The implementation for the proposed method was carried out in an IC assembly factory in Taiwan; results in this study demonstrate the practicability of the proposed approach     

应用于微系统封装的激光局部加热键合技术

阐述了利用激光与物质相互作用的热效应实现微系统器件的局部加热键合原理，提出了激光键合塑料芯片和激光辅助加热阳极键合的思想，建立了半导体激光键合实验装置，并实现了聚甲基丙烯酸甲酯(PMMA)之间的键合。     

应用于微系统封装的激光局部加热键合技术

阐述了利用激光与物质相互作用的热效应实现微系统器件的局部加热键合原理 ,提出了激光键合塑料芯片和激光辅助加热阳极键合的思想 ,建立了半导体激光键合实验装置 ,并实现了聚甲基丙烯酸甲酯 (PMMA)之间的键合     

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.     

Room-temperature microfluidics packaging using sequential plasma activation process

A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical plasma was applied for microfluidics packaging at room temperature. Si/glass and glass/glass wafers were activated by the oxygen RIE plasma followed by nitrogen microwave radicals. Then, the activated wafers were brought into contact in atmospheric pressure air with hand-applied pressure where they remained for 24 h. The wafers were bonded throughout the entire area and the bonding strength of the interface was as strong as the parents bulk wafers without any post-annealing process or wet chemical cleaning steps. Bonding strength considerably increased with the nitrogen radical treatment after oxygen RIE activation prior to bonding. Chemical reliability tests showed that the bonded interfaces of Si/Si could significantly withstand exposure to various microfluidics chemicals. Si/glass and glass/glass cavities formed by the sequential plasma activation process indicated hermetic sealing behavior. SiO/sub x/N/sub y/ was observed in the sequentially plasma-treated glass wafer, and it is attributed to binding of nitrogen with Si and oxygen and the implantation of N/sub 2/ radical in the wafer. High bonding strength observed is attributed to a diffusion of absorbing water onto the wafer surfaces and a reaction between silicon oxynitride layers on the mating wafers. T-shape microfluidic channels were fabricated on glass wafers by bulk micromachining and the sequential plasma-activated bonding process at room temperature.     

Optimization of the Cu wire bonding process for IC assembly using Taguchi methods

The yield of IC assembly manufacturing is dependent on wire bonding. Recently, the semiconductor industry demands smaller IC designs and higher performance requirements. As such, bonding wires must be stronger, finer, and more solid. The cost of gold is continuously appreciating, and this has become a key issue in IC assembly and design. Copper wire bonding is an alternative solution to this problem. It is expected to be superior over Au wires in terms of cost, quality, and fine-pitch bonding pad design. To obtain the best wire bonding quality, we employed Taguchi methods in optimizing the Cu wire bonding process. With Cu wire bonding technology, the production yield increased from 98.5% to 99.3% and brought approximately USD 0.7 million in savings.     

Development of a thermal resistance model for chip-on-board packaging of high power LED arrays

The performance of high power LEDs strongly depends on the junction temperature. Operating at high junction temperature causes degradation of light intensity and lifetime. Therefore, proper thermal management is critical for LED packaging. While the design of the heat sink is a major contributor to lowering the overall thermal resistance of the packaged luminaire, another area of concern arises from the need to address the large heat fluxes that exist beneath the die. In this study we conduct a thermal analysis of high power LED packages implementing chip-on-board (COB) architecture combined with power electronic substrate focusing on heat spreading effect. An analytical thermal resistance model is presented for the LED array and validated by comparing it with finite element analysis (FEA) results. By using the analytical expression of thermal resistance, it is possible to understand the impact of design parameters (e.g., material properties, LED spacing, substrate thickness, etc.) on the package thermal resistance, bypassing the need for detailed computational simulations using FEA.     

Localized bonding processes for assembly and packaging of polymeric MEMS

Localized bonding schemes for the assembly and packaging of polymer-based microelectromechanical systems (MEMS) devices have been successfully demonstrated. These include three bonding systems of plastics-to-silicon, plastics-to-glass, and plastics-to-plastics combinations based on two bonding processes of localized resistive heating: 1) built-in resistive heaters and 2) reusable resistive heaters. In the prototype demonstrations, aluminum thin films are deposited and patterned as resistive heaters and plastic materials are locally melted and solidified for bonding. A typical contact pressure of 0.4 MPa is applied to assure intimate contact of the two bonding substrates and the localized bonding process is completed within less than 0.25 s of heating. It is estimated that the local temperature at the bonding interface can reach above 150/spl deg/C while the substrate temperature away from the heaters can be controlled to be under 40/spl deg/C during the bonding process. The approach of localized heating for bonding of plastic materials while maintaining low temperature globally enables direct sealing of polymer-based MEMS without dispensing additional adhesives or damaging preexisting, temperature-sensitive substances. Furthermore, water encapsulation by plastics-to-plastics bonding is successfully performed to demonstrate the capability of low temperature processing. As such, this technique can be applied broadly in plastic assembly, packaging, and liquid encapsulation for microsystems, including microfluidic devices.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame.The gold wire bonding process has been widely used in LED packaging industry currently.However,due to the high cost of gold wire,copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving.In this paper,the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation.This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Understanding a semiconductor process using a full-scale model

A full-scale semiconductor manufacturing plant model was developed from a SEMATECH dataset using the computer software package EXTEND. The model was generated to study the complex interactions and characteristics of a semiconductor fabrication process. Equipment downtimes, process flow routes, and machine processing times were used to validate the model. Pilot runs of the model were used to determine simulation run times and data collection rates for the initial inventory and product cycle time measurements. The product cycle time results from the model at 95% capacity were within 63 hours (or 7%) of the SEMATECH cycle time measurements. These results demonstrate the accuracy of the simulation model built from the SEMATECH dataset. The full-scale model was set up to run special scenarios showing the effects of eliminating maintenance and changing product types. The full-scale model was compared to a small-scale model based on the same dataset to demonstrate the inadequacy of the validated small-scale model. A full-scale model is also useful for analyzing scheduling routines, detecting bottlenecks, and understanding machine relations in the semiconductor industry     

Clock synchronization using a linear process model

In this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least‐squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals. Copyright © 2006 John Wiley & Sons, Ltd.     

Texture classification using a spatial-point process model

A Bayesian statistical classifier for the segmentation of texture is presented, which models the quantised image data as a set of independent spatial Poisson processes. Two data sets are examined, namely Gaussian white noise textures, and textures contained in a sidescan sonar image of the seabed. The Poisson model is demonstrated to be applicable in both these cases, and a maximum likelihood discriminant function is developed. Finally, results are presented for the classification of both data sets     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.