一种高性能超低功耗亚阈值基准电压源

设计了一种超低功耗、无片上电阻、无双极型晶体管的基于CMOS亚阈值特性的基准电压源。采用Oguey电流源结构来减小静态电流,从而降低功耗,并加入工作于亚阈值区的运算放大器,在保证低功耗的前提下,显著提高了电源电压抑制比。采用1.8 V MOS管与3.3 V MOS管的阈值电压差进行温度补偿,使得输出电压具有超低温度系数。采用共源共栅电流镜以提高电源电压抑制比和电压调整率。电路基于SMIC 0.18 μm CMOS工艺进行设计和仿真。仿真结果表明,在－30 ℃~125 ℃温度范围内,温漂系数为9.3×10－6/℃;电源电压为0.8~3.3 V时,电压调整率为0.16%,电源电压抑制比为－58.2 dB@100 Hz,电路功耗仅为109 nW,芯片面积为0.01 mm²。     

Designing efficient FPGA tiles for power-constrained ultra-low-power applications

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%.     

基于FPGA的数据高速串行通信实现

针对FPGA在音、视频传榆中的特性,提出两种基于FPGA的数据高速串行同步传输的方法,并用Altera公司的ACEX1K系列器件完成相应编码解码的程序设计.这两种恢复同步时钟的方法与传统的锁相环方法相比,实现更简单,建立时间更短,对系统时钟要求更低.     

基于FPGA实现的高速数据采集系统及其在有源电力滤波器中的应用

有源电力滤波器(APF)是抑制谐波的主要手段之一,其谐波检测环节要求高速采集多路数据.现场可编程门阵列FPGA(Field Programmable Gate Array)器件具有资源丰富、接口灵活等特点,基于FPGA和快速A/D转换器,AD7864提出一种高速数据采集电路,并给出其程序控制算法,通过实验验证其采样效果良好,能够满足APF对信号采样的实际要求.     

数字签名算法MD5的FPGA高速实现

信息安全在网络发展中非常重要。信息验证是验证信息来源的基本技术。常用的信息验证码是使用单向散列函数生成验证码。使用FPGA高速实现MD5认证算法,协处理器用Xilinx公司的Virtex系列FPGA,以PCI卡形式处理认证服务。     

Xilinx低等级FPGA高可靠应用的升级试验方法研究

随着微电子设计与制造水平的不断提高,部分低质量等级集成电路逐渐地具备了应用于高可靠性要求的军事和宇航领域的能力。Xilinx FPGA作为高性能逻辑器件的典型代表,具有较高的设计和工艺成熟度,在军事和宇航领域有着广阔的应用前景。全面梳理了Xilinx FPGA质量等级的定义规则,详细介绍了Xilinx不同质量等级FPGA的厂家保证情况,提出了Xilinx低质量等级FPGA面向高可靠应用的升级试验方法。     

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

基于FPGA和USB的高速数据传输、记录及显示系统

提出了一种基于FPGA和USB的高速数据传输、记录及显示系统的设计方案，并对其中的低电压差分信号(LVDS)传输方式、FPGA功能模块以及USB传输模块等进行了介绍。该系统不但可以快速方便的传输、记录及显示雷达数据形成分机的数据，还具有判断数据帧头错误、帧长度错误的功能。     

一种采用噪声抵消及多重功耗优化技术的UWB-LNA

采用噪声抵消及多重功耗优化技术,提出了一种超宽带低噪声低功耗放大器。它主要包括采用RL网络的共栅输入级、电流复用型噪声抵消级、放大输出级以及偏置电路四个部分。验证结果表明,该放大器,在2-6GHz频带内,增益(S21)可以在14dB以上;输入回波损耗(S11)小于-10dB;输出回波损耗(S22)小于-25dB;噪声系数(NF)小于3.2dB;在3.8V的工作电压下,功耗仅为14mW。     

单片电路应用的超低功耗E型GaAs MESFET研究

本文从器件的几何、材料和工艺参数出发，获得了低功耗低噪声增强型ＧａＡｓＭＥＦＥＴ模型的等效电路元件值。研究了器件的几何、材料和工艺参数及ＲＦ性能和直流功耗的关系，给出了ＥＦＥＴ物理参数的最佳取值范围，可为超低功微订成电路中有源器件的设计提供依据。     

FPGA中DCM工作原理及其在高速ADC电路中的应用

简述了Xilinx公司Virtex系列FPGA中数字时钟管理器(DCM)的工作原理,以及在高速ADC输出数据同步处理电路中的应用。给出采用DCM进行高速数据同步处理方法,数据同步时钟相位调节的方法和试验结论。     

基于FPGA的智能热水器设计

传统电热水器系统大多采用单片机作为控制核心,仅具有加热和保温功能,水温不可见,水量不易控制,大多热水器在保温时采用开关控制,给电力系统带来巨大冲击。本系统选用现场可编程逻辑器件ActelFusion系列FPGA作为控制核心,充分利用其内部模数混合的特点实现水温数字可视化、可预约时间等等功能,运用PID算法实现水的加热和保温,使电力系统受到很小的冲击,且该系统具有安全可靠、节能、高效能、性能稳定、简易操作的特性。     

基于DSP+FPGA的高速数字信号处理平台的电源设计

介绍了一种高速数字信号处理平台的电源设计实现方案,主要是基于FPGA DSP的结构实现高速数字信号处理。该方案采用先进的FPGA,DA转换器和DSP芯片,通过对DSP芯片和FPGA芯片及DA芯片的正确供电和电源监控来实现具有通用性、可扩充性的硬件平台,并对电源设计中的多项关键参数进行分析与阐述。     

高速移动下OFDM均衡器的FPGA实现

在高速移动下,OFDM系统载波间正交性被破坏,出现载波间干扰（ICI）,严重影响系统性能,必须采用适当的均衡技术以补偿ICI。为了保证通信的有效性和实时性要求,使用FPGA实现了一种低复杂度的最小均方误差（MMSE）OFDM均衡器算法。在ISE软件平台上使用Verilog语言编写程序,并在Xilinx公司Virtex-2实验板（XC2V930芯片）上对设计进行了验证。     

基于MCU和FPGA的三相高精度程控电源

简述了目前程控电源的现状和FPGA在实现闭环PID控制方面的优势,提出了将直接数字频率合成技术（DDS-Digital Direct Frequency Synthesis）和PID控制技术相结合来设计程控电源,介绍了系统各个模块,并分析了FPGA实现DDS和PID的原理与方法,通过实验测试证明该方法的可行性。实践证明...     

基于FPGA的视频图像画面分割器设计

为了解决在一个屏幕上收看多个信号源的问题,对基于FPGA技术的视频图像画面分割器进行了研究。研究的主要特色在于构建了以FPGA为核心器件的视频画面分割的硬件平台,首先,将DVI视频信号,经视频解码芯片转换为数字视频图像信号后送入异步FIFO缓冲。然后,根据画面分割需要进行视频图像数据抽取,并将抽取的视频图像数据按照一定的规则存储到图像存储器。最后,按照数字视频图像的数据格式,将四路视频图像合成一路编码输出,实现了四路视频图像分割的功能,提高了系统集成度,并可根据系统需要修改设计和进一步扩展功能,增加了系统的灵活性,适用于多种不同领域。     

一种适用于在FPGA中实现频域均衡的高精度FFT结构

本文简单介绍了频域均衡基本原理 ,并针对其在 FPGA中的实现提出了一种基于频率抽取算法的 FFT实现结构。此结构具体服务于 2 5 6点基二 FFT变换 ,为充分满足在FPGA中实现频域均衡的要求 ,具有占用硬件资源合理 ,计算精度高的特点     

High speed,low power VLSI CMOS vision sensor for geometric centre object tracking

In this article an object tracking CMOS sensor is presented. The architecture incorporates photo detection devices and pixel level processing elements for capturing and processing the image data and extracting the object's coordinates. The edges of the image scene are extracted by in-pixel edge detectors and the region (object) of interest, selected by the user, is segmented using a switch network. Coordinates of the desired region are obtained by extracting the geometric centre of the region. Tracking of the selected object is then performed by automatic reselection of the region using the updated coordinates. The proposed design presents less sensitivity to threshold adjustments than binarisation techniques. The sensor has been designed as a 64 × 64 pixel VLSI CMOS chip in the 0.35 μm standard CMOS technology. The proposed structure is analysed with regard to its operation in the presence of mismatches and noise. Features of the sensor are reported and compared with some previous object tracking designs. Because the power dissipation is small, the chip is ideal for low-power applications.     

适合FPGA平台的由高数据速率软件界定的无线电接收器

Although Alternate Parallel Receiver （APRX） could effectively improve the maximum demodulating rate of the receiver, its frequency domain processing module consumes a large amount of multiplication units when the number of parallel input channels is large, making it unsuitable for use on FPGA software defined radio platforms. This paper proposes an optimization scheme by introducing partitioned convolution and exploring the spectrum characteristic of the APRX input data, reducing the usage of multipliers greatly. After the optimization, the number of real multipliers used in the frequency-domain processing module of the 16-ary APRX is reduced from about 576 to 68, with little performance loss. This optimized APRX is fairly suitable for FPGA software defined radio platform applications.     

FPGA vs. ASIC for low power applications

Field Programmable Gate Array (FPGA) are becoming more and more popular and are used in many applications. However, it is well known that the performance is limited comparing to full ASIC implementation, but for many applications the speed requirements fit the ones provided already by existing FPGA circuits. Power consumption seems to be one of the most important limiting factor and so far it is in favour of Application Specific Integrated Circuits (ASIC) [Varghese Georges, Jan M. Rabaey, Low-Energy FPGA, Architecture and Design, Kluwer Academic Publishers, 2001; Tadahiro Kuroda, Power-Aware Electronics: Challenges and Opportunities, Tutorial at FTFC 2003, Paris, May 2003]. In this paper, we will present results obtained by characterizing various circuits implemented using both FPGA and ASIC technologies in order to determine the power consumption ratio and evaluate the efficiency of the power optimization techniques such as clock gating [Amara AMARA, Philippe Royannez, VHDL for Low Power, (Chapter 11), Low Power Electronics Design, Edited by Christian Piguet, CRC Press 2005; Luca Benini, Giovanni De Micheli, Dynamic Power Management, Kluwer Academic Publishers, 1998].We have started a study in order to compare the power consumption of two Intellectual Property (IP), a counter circuit and an image transform circuit. Both circuits have been implemented using FPGA Family circuits from ALTERA and Hardware Copy of the circuits which are close to the ASIC implementation. A full ASIC implementation using UMC 0.13 μm have be also characterized in terms of power.FPGA power consumption estimation flow is based on ALTERA tools (QuartusII) that provide accurate overall power consumption for a set of input stimuli, on various targets: FPGA families and Hardware Copy. ASIC power consumption estimation flow is based on Synopsys Power tools.