Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

部分耗尽0.8μm SOI CMOS工艺P+源漏电阻实验设计

文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验指出注入能量未处于合理的范围,导致源漏电阻工艺窗口不足,影响0.8μm SOI工艺成品率。通过实验优化后部分耗尽0.8μm SOI CMOS工艺P+源漏电阻达到小于200Ω/□,工艺能力显著提高到Ppk>2.01水平,充分满足部分耗尽0.8μm SOICMOS工艺P+源漏电阻需求。     

GaAs MQW modulators integrated with silicon CMOS

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

Reliability aspects of thermal micro-structures implemented on industrial 0.8 μm CMOS chips

This paper discusses the reliability characterization of thermal micro-structures implemented on industrial 0.8 μm CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. At high temperatures the mechanisms are many and varied, and co-incidental thermally-induced mechanical defects are found in both the poly-Si heater and the poly-Si temperature sensor, along with temperature- and current-enhanced interlayer diffusion degradation of the heater contacts. Local reduction in the device thermal capacity by using silicon micro-machining can be expected to hold the promise of a number of significant advantages, especially for limiting current stressing of the contact regions. The results can be used to optimize the design of thermally based micro-sensors on CMOS chips, such as CMOS compatible chemoresistive gas sensors.     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

CMOS图像传感器中RSD A/D转换器的设计与实现

提出了CMOS图像传感器中RSD A/D转换器的设计方法.基于冗余符号数(RSD)算法,RSD A/D转换器降低了对比较器的性能要求.并且全差分的模拟信号处理用以改进抗噪声度,信噪比和系统的动态范围.RSD A/D转换器是基于90 nm CMOS工艺实现的,测试结果表明它的微分非线性误差(DNL)为±1 LSB,积分非线性误差(INL)为±1.5 LSB,总的未调整误差(TUE)为-3 LSB～1 LSB,功耗约为20 mW.     

Doping of semiconductor devices by Laser Thermal Annealing

In today's highly competitive semiconductor industry, and due to the accelerating pace of technology development, the integration of new and disruptive solutions to address process limitations is a mandatory requirement, although most challenging, Doping, i.e. the ability to control material properties locally and by extension local strain engineering, are amongst the key process variables used to overcome device performance issues. With the emergence of three-dimensional (3D) devices and architectures at the nanoscale, new doping schemes which rely on low thermal budgets are being evaluated, especially in the framework of new materials introduction such as germanium (Ge) and III-Vs in front end logic, defect engineered oxides and phase change materials in memory, or silicon carbide (SiC) and gallium nitride (GaN) in power devices.Ultrafast sub-µs annealing schemes with shallow penetration depths providing localized impact, such as Laser Thermal Anneal (LTA), are some of the most promising and scalable approaches being evaluated today. Its production worthiness is already established as process of record for high volume manufacturing of several 3D stacked architectures such as vertical silicon (Si) and SiC power devices and complementary-metal-oxide-semiconductor (CMOS) imaging sensors.This paper reviews recent work highlighting the potential of LTA as an enabler for next generation technologies covering a wide range of applications from Logic to Nano-Electro-Mechanical Systems (NEMS) and 3D sequential integration.     

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module.First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach.A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV.Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development.The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price.Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure.In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance.To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!     

3D Out‐of‐Plane Rotational Etching with Pinned Catalysts in Metal‐Assisted Chemical Etching of Silicon

Pinned structures in conjunction with shaped catalysts are used in metal‐assisted chemical etching (MACE) of silicon to induce out‐of‐plane rotational etching. Sub‐micro‐ and nanostructures are fabricated in silicon, which include scooped‐out channels and curved subsurface horns, along with vertically oriented thin metal structures. Five different etching modes induced by catalyst and pinning geometry are identified: 1) fully pinned–no etching, 2) rotation via twist, 3) rotation via delamination, 4) in‐plane bending, and 5) swinging. The rotation angle is roughly controlled through catalyst geometry. The force and pressure experienced by the catalyst are calculated from the deformation of the catalyst and range between 0.5–3.5 μN and 0.5–3.9 MPa, respectively. This is a new, simple method to fabricate 3D, heterogeneous sub‐micro‐ and nanostructures in silicon with high feature fidelity on the order of tens of nanometers while providing a method to measure the forces responsible for catalyst motion during MACE.     

A comparative study of CMOS processes for VLSI applications

A comparative study of simulated circuit performance has been made in order to determine the optimum process parameters for p-well CMOS with feature sizes of between 1 and 2 µm. it has been found that for the process considered, best speed, Power, and packing density are achieved with a substrate concentration of between 3 × 10¹⁵and 10¹⁶cm^-3and an operating voltage which is as low as possible. Higher speed can be attained at the expense of considerably more power dissipation through the use of a higher rail voltage. Silicon-on-insulator CMOS has been considered as an alternative to p-well CMOS. This technology can be expected to out-perform small geometry bulk silicon CMOS if recent improvements in material quality can be maintained.     

Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

We present the integration scheme we have optimized to fabricate very short gate length MOSFETs with 2D and 3D arrays of silicon nanowires (NW) and higk-k/metal gate stacks. Aggressively scaled NWs with sub-5 nm diameters are obtained. In particular, we report a 3D matrices technology with up to 13 levels of stacked single-crystal Si nanowires that can be most interesting for memory applications. In addition, we present a careful study of the electrical properties of such devices. Our electrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties. We identify peculiar transport and interface properties and we show that surface effects are significant for diameters equal or lower than 20 nm. The use of nanowires (whatever the process) in standard sub-11 nm CMOS nodes circuits will depend mainly on lithography progress in the coming years, but also on contact and metal interconnects. Ultra dense 3D arrays of Si nano-wires can however be fabricated in R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization.     

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

The operational speed and power dissipation of scaled one-transistor RTD/HFET memories

The scaling behaviour of a memory that uses resonant tunnelling diodes (RTDs), namely the one-transistor tunnelling SRAM (TSRAM), is compared with the dominant memory technology, silicon CMOS. The minimum feature size (MOSFET or HFET gate length λ) is scaled in the range from 500 nm to 50 nm. Appropriate scaling laws are used for the RTD and wiring elements. We set up a benchmark architecture that we have modelled in RTD/HFET and in silicon CMOS, and simulated with HSPICE, in order to determine the limits on operational frequency. The RTD-based memories show speeds about an order of magnitude higher than the equivalent CMOS memory, even for very large memories. The performance improves with smaller values of λ and smaller memory sizes. However, for larger memories, the power dissipation outside TSRAM memory cells is still very high for enhancement/depletion (E/D) HFET circuitry.     

Shallow trench isolation based on selective formation of oxidized porous silicon

We have studied the porous silicon (PS) formation dependence on the substrate doping concentration as a selective tool to form locally oxidized regions in silicon wafers. This approach could be used for electrical isolation in CMOS circuits as a promising alternative to the shallow trench isolation STI process which begins to show some limitations (voiding and dishing) for the most advanced technologies.     

Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks

Per-flow queueing with sophisticated scheduling is one of the methods for providing advanced quality of service (QoS) guarantees. The hardest and most interesting scheduling algorithms rely on a common computational primitive, implemented via priority queues. To support such scheduling for a large number of flows at OC-192 (10 Gb/s) rates and beyond, pipelined management of the priority queue is needed. Large priority queues can be built using either calendar queues or heap data structures; heaps feature smaller silicon area than calendar queues. We present heap management algorithms that can be gracefully pipelined; they constitute modifications of the traditional ones. We discuss how to use pipelined heap managers in switches and routers and their cost-performance tradeoffs. The design can be configured to any heap size, and, using 2-port 4-wide SRAMs, it can support initiating a new operation on every clock cycle, except that an insert operation or one idle (bubble) cycle is needed between two successive delete operations. We present a pipelined heap manager implemented in synthesizable Verilog form, as a core integratable into ASICs, along with cost and performance analysis information. For a 16 K entry example in 0.13-mum CMOS technology, silicon area is below 10 mm² (less than 8% of a typical ASIC chip) and performance is a few hundred million operations per second. We have verified our design by simulating it against three heap models of varying abstraction     

A comparison between plasma charging-damage and inductive-damage: Damage response to Fowler-Nordheim stress

This paper reports on the results of a study performed to compare the effects of charging damage and inductive damage to 0.5 μm n-channel MOSFETs arising from plasma etching at the gate-definition etch and metal-1 etch levels, respectively. The MOSFETs were fabricated on 200 mm p/p+ silicon wafers using a full CMOS process. The gate-definition etch step was performed using a chlorine-based chemistry and the metal etch step was done using a BCl₃/N₂/Cl₂ plasma. It is found that charging damage is electrically inactive after the full CMOS process flow; however, it is electrically activated by Fowler-Nordheim (F-N) stress when charging damage is clearly seen to correlate with the area of charging antenna in the device. Inductive damage, on the other hand, is seen to impact transistor parameters directly after the CMOS process and before the application of F-N stress. This is attributed to distinctly different mechanisms that are responsible for the creation of the two types of damage: charging damage arises from a dc current stress, whereas inductive damage is suggested to arise from ac current stress.     

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifierfor an optical receiver, fabricated it in several different minimumfeature sizes of standard digital CMOS, and demonstrated designscaleability of this analog integrated circuit design. The sameamplifier was fabricated in a 1.2 µm and two different0.8 µm processes through the MOSIS foundry [1].The amplifier uses a multi-stage, low-gain-per-stage approach.It has a total of 5 identical cascaded stages. Each stage isessentially a current mirror with a current gain of 3. Threeof these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with anInGaAs MSM detector by using a thin-film epilayer device separationand bonding technology [2]. This quasi-monolithic front-end of anoptical receiver virtually eliminates the parasitics between thephotodetector and the silicon CMOS preamplifier. We have demonstratedspeed and power dissipation improvement as the minimum feature sizeof the transistors shrink.     

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.