Transistor realization of reversible “ZS” series gates and reversible array multiplier

In order to reduce the redundant Toffoli gates and the line-crossings in the classical reversible full adder appearing in the present literatures, this paper gives a reconstructive structure of Fredkin gate, called RF gate, the corresponding quantum equivalent realization and electronic circuitry construction based on CMOS technology and pass-transistor of this gate are also designed in this paper. With the assistance of the RF gate and the basic reversible gates (including NOT gate, CNOT gate and Toffoli gate), we design new 4×4 reversible gates called “ZS” series gates and its corresponding electronic circuitry construction. The proposed “ZS” series gates have the ability to operate reversible add operation between two signed numbers by a single gate and at lower power consumption. At the same time, as an application of “ZS” series gates, this paper also designs reversible array multiplier in order to achieve the signed multiplication. It can be theoretically proved that the proposed reversible array multiplier can eliminate power loss associated with the irreversible operation of classical computer, and will be exponentially lower than reversible parallel multiplier with respect to time complexity.     

Computational analysis and comparison of reversible gates for design and test of logic circuits

Quantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.     

基于可编程逻辑器件的高速乘法器IP设计

介绍了一个八位高速并行乘法器的IP设计。该乘法器的部分积产生电路采用非重叠的三位编码方式，并且改进了Wallace加法树内部的连线方式，用VHDL语言描述了整个设计，并在Altera公司EPF10K10LC84－3上实现了该乘法器。     

4-2 compressor of fast booth multiplier for high-speed RISC processor

A 4-2 compressor for a fast booth multiplier is designed and optimized by two circuits configurations one is constructed of different but optimized XOR circuits with 44 transistors and a total transistor size W/L of 574. The other one is made of single to dual rail transmission gates (TGs) with 56 transistors and a total transistor size W/L of 467. The maximum propagation delay, the power consumption and the chip (layout) area of the two configuration 4-2 circuits are simulated with 0.3?μm and 0.2?μm CMOS process parameters. The results show that the delay and power consumption of circuits with 0.2?μm technology are smaller than those of circuits with 0.3?μm technology. Also, 4-2 circuits are synthesized. This is supported by 0.2?μm CMOS library and design compiler (DC) software (Tools) and compared with the proposed circuits of this research, the designed TG 4-2 compressor is faster and area smaller than that of synthesized one, so the designed TG 4-2 compressors can be optimized for high speed and small chip area applications when compared with the synthesized structures.     

Novel CMOS multi-bit counter for speed-power optimization in multiplier design

The paper introduces a novel multi-bit counter for efficient binary multiplication. A 7:3 counter is proposed, customized and optimized by 3-pronged approach, firstly by group-wise parallel addition using half-adders, secondly by eliminating redundant carry-generators from the design and finally, by optimizing the resultant hardware. The circuit is designed and optimized on standard static-CMOS. Corner analyses with TT, FF and SS for PVT-variation have been performed on proposed design to study reliability and robustness. A benchmarking exercise on Power-Delay-Product (PDP) with reported candidate designs demonstrates superiority of the proposed design. The study reveals that the 7:3-counter, designed using proposed strategy, has up to 36% less PDP, compared to the best candidate-design. Next, the proposed counters are employed, first to design an 8-b × 8-b Column-Compression (CC) multiplier and thereafter, using decomposition-logic on thus-designed-8-b × 8-b-multipliers, to design a 16-b × 16-b multiplier. The multipliers are optimized on 90-nm standard-CMOS technology and compared for speed-power performance with reported candidate designs at 500 MHz. Simulations show that the presented design of 16-b × 16-b multiplier using proposed 7:3 counter offers 55% less PDP, compared to the best candidate design under identical conditions. Once again, all simulations are performed on TSMC 90-nm CMOS technology at 25 °C temperature and 1.0 V supply-rail.     

传感器电路中乘法器噪声模型分析

本文对两输入端都带噪声情况下乘法器的响应进行了理论推导,得到其噪声模型:乘法器输出噪声包括载波携带信号噪声项、信号携带载波噪声项以及噪声相乘项.设计传感器电路时,通过提高载波纯度及其幅度、在信号输入端加性能优良的带通滤波器,可以得到优异的噪声性能.本文用实验验证了该模型的正确性.     

Research of fast modular multiplier for a class of finite fields

A new structure of bit-parallel Polynomial Basis（PB）multiplier is proposed,which is based on a fast modular reduction method.The method was recommended by the National Institute of Standards and Technology（NIST）.It takes advantage of the characteristics of irreducible polynomial,i.e.,the degree of the second item of irreducible polynomial is far less than the degree of the polynomial in the finite fields GF（2^m）.Deductions are made for a class of finite field in which trinomials are chosen as irreducible polynomials.Let the trinomial be x^m＋x^k＋1,where 1 ≤k≤[m/2].The proposed structure has shorter critical path than the best known one up to date,while the space requirement keeps the same.The structure is practical,especially in real time cryptographic applications.     

基于16位定点DSP的并行乘法器的设计

设计了一种用于1 6位定点DSP中的片内乘法器.该乘法器采用了改进型Booth算法,使用CSA构成的乘法器阵列,并采用跳跃进位加法器实现进位传递,该设计具有可扩展性,并提出了更高位扩展时应改进型方向.设计时综合考虑了高性能定点DSP对乘法器在面积和速度上的要求,具有极其规整的布局布线.     

数字信号处理器中阵列乘法器的研究与实现

文章讨论了基本的线形阵列加法器和基于水平压缩矩阵的并行阵列加法器，在此基础上提出了一种改进的阵列乘法器结构．通过生成多位的部分积，大大减少进位传输的延迟，提高乘法器的速度，并通过对三种结构的实现效率进行对比得到了验证。     

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability.     

Trading off circuit lines and gate costs in the synthesis of reversible logic

Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large.     

基于可逆逻辑电路的脉冲分配器设计

可逆逻辑电路能大幅度降低能耗,越来越受到研究人员重视。运用可逆逻辑电路对传统脉冲分配器进行可逆设计,并提供了物理实现方法。首先对传统的脉冲分配器中的触发器和计数器进行可逆设计,然后将传统脉冲分配器的中的计数器进行替换,最后将可逆计数器和译码器级联,从而构建可逆脉冲分配器。仿真结果表明实现了脉冲分配器的功能。     

A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

We present a new serial-parallel concurrent modular-multiplication algorithm and architecture suitable for standard RSA encryption. In the new scheme, multiplication is performed modulo a multiple of the RSA modulus n, which has a diminished-radix form 2 ^k -v, where k and v are positive integers and v < n. This design is the first concurrent modular multiplier to use a diminished-radix algorithm and to pipeline concurrent modular-reduction to optimize the clock rate. For a modular multiplier of order ranging from 1 to 10 (number of multiplier bits per clock cycle), a faster clock rate and throughput is possible than with other known designs including those of Brickell, Morita, Sedlak and Golze, and Miyaguchi. Throughput estimates for 512-bit RSA decryption range from 100 kbit/s in a serial mode to 650 kbit/s with a modular multiplier of order 10, at a clock rate of 20 MHz on 1.5 m CMOS.     

Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

Parallel multiplier is one of the most important building blocks in all the DSP processors, which needs faster computations. To reduce the total transistor count in a multiplier we have proposed two new approaches. The first approach is using a 26 transistor booth encoder and a 8-transistor/partial-product booth selector to generate partial products. The second approach proposes a new circuit for 4 : 2 compressors. The booth encoder and booth selector reported here are the smallest in transistor count, but comparable to the best delay with less power consumption. This paper describes a comparison of a compact 16 × 16 parallel multiplier using the new circuit components. This shows a transistor count advantage of 27% and 52% in partial product generation and partial product accumulation, respectively.     

原始状态在时序逻辑电路设计中的应用研究

原始状态的确定对于时序逻辑电路的设计而言十分重要,本文通过对设计实例设计过程中原始状态的分析和确定,完善了时序逻辑电路的设计步骤,使时序逻辑电路的设计思路更加清晰。     

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90 nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13 ns while the power consumption of the same was ∼58.82 mW for a layout area of ∼6 mm². Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.     

卡诺图在数字电路分析和设计中的应用

卡诺图是数字电路中非常重要的分析和设计工具。通过若干实例,揭示了卡诺图的直观性和实用性,系统全面地掌握卡诺图的各种应用,可以大大简化数字电路分析和设计的过程,起到事半功倍的效果。     

用于空气中障碍检测的超声相控阵发射电路设计

设计了一种针对空气环境下障碍检测的超声相控阵发射电路.使用DSP Builder结合Matlab与quartusⅡ在FPGA平台上完成基于DDS技术的信号发生器设计,得到相位分辨为1.41°、幅值分辨率为0.1V的40kHz正弦波信号.设计了中心频率40kHz、带宽15kHz的二阶带通滤波电路及输出功率可达17W的放大电路,并利用Orcad软件对上述两种电路进行了Spice仿真验证.     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计. 该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法. 还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tile-based FPGA 芯片设计所加的约束. 该乘法器可以配置成同步或异步模式,也可以配置成带流水线的模式以满足高频操作. 该设计很容易扩展成不同的输入和输出位宽. 同时提出了一种新的超前进位加法器电路来产生最后的结果. 采用了传输门逻辑来实现整个乘法器. 乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns. 全部使用2级的流水线时,时钟周期可以达到2.5ns. 这比商用乘法器快29.1%,比其他乘法器快17.5%. 与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.