A study on the tensile fracture mechanism of 15 μm copper wire after EFO process

In this study, 15 μm copper wires were bonded on substrates with thermosonic process, and the tensile fracture characteristics of FAB, as well as bonded samples, were investigated. For electronic packaging applications, all 15 μm wires were fully annealed, and the microstructures consisted of equiaxed grains. After EFO (electric flame-off) process, the microstructure of wire can be divided into three parts: (1) free air ball (FAB) with columnar grains, (2) heat-affected zone (HAZ) with equal-diameter grains, (3) annealing zone with equiaxed grains. According to tensile test results, EFO process simultaneously reduced UTS and elongation of the wire. For both FAB and bonded samples, the tensile fracture zones were either in the region of equal-diameter grains or in coarse grains located within 100 μm from the ball. And it was observed that the breakage sites appeared near the twins and the columnar grains when tensile fracture happened. Meanwhile, the relationship between hardness and microstructure of wires after EFO process were analyzed with nano-indentation. The nano-hardness value of 15 μm wire was 1.2-1.45 GPa.     

An ultra-wide-band 3.1-10.6 GHz LNA design in 0.18 μm SiGe BiCMOS

A two-stage monolithic ultra-wide-band (UWB) low-noise-amplifier (LNA) designed for MB-OFDM in 0.18 μm SiGe BiCMOS process is presented. With an optimized configuration combining advantages of RES-feedback and LC-ladder matching structure, the adjustable wide input matching is got and noise figure (NF) is controlled to a relevant low status. The measured S21 is from 7.6 to 14.2 dB over the 3-11 GHz operating band, NF is from 3.2 dB to 4.8 dB. With a 2.5 V power supply, the LNA has an overall power consumption of 14.5 mW.     

Measurements of charge carrier mobilities and drift velocity saturation in bulk silicon of 〈1 1 1〉 and 〈1 0 0〉 crystal orientation at high electric fields

The mobility of electrons and holes in silicon depends on many parameters. Two of them are the electric field and the temperature. It has been observed previously that the mobility in the transition region between ohmic transport and saturation velocities is a function of the orientation of the crystal lattice.This paper presents a new set of parameters for the mobility as function of temperature and electric field for 〈1 1 1〉 and 〈1 0 0〉 crystal orientation. These parameters are derived from time of flight measurements of drifting charge carriers in planar p⁺nn⁺ diodes in the temperature range between −30 °C and 50 °C and electric fields of 2 × 10³ V/cm to 2 × 10⁴ V/cm.     

Non-linear properties of nitride-based nanostructures for optically controlling the speed of light at 1.5 μm

Future bandwidth demand in optical communications requires all-optical devices based on optical non-linear behavior of materials. InN, with a room temperature direct bandgap well below 0.82 eV (1.5 μm) is very attractive for these applications. In this work, we characterize the non-linear optical response and recombination lifetime of the interband transition of InN layers grown on GaN template and Si(1 1 1) by molecular beam epitaxy. Non-linear characterization shows a decrease of the third-order susceptibility, χ⁽³⁾, and an increase of recombination lifetime when decreasing the energy difference between the excitation and the apparent optical band-gap energy of the analysed samples. Taking into account the non-linear characterization, an optically controlled reduction of the speed of light by a factor S=4.2 is obtained for bulk InN at 1.5 μm. The S factor of InN (5 nm)/In_0.7Ga_0.3N (8 nm) multiple quantum well heterostructures at the same operation wavelength is analysed, predicting an increase of this factor of three orders of magnitude. This result would open the possibility of using InN-based heterostructures for all-optical devices applications.     

Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A

Compact modeling of MOSFETs from a 0.35 μm SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more accurately reproduce measured DC behavior, which is not possible with the standard BSIM model set. The model presented exhibits convergent behavior and is shown to be experimentally accurate at 4 K. No design tool currently in place exhibits convergence and/or accuracy over this range. The Verilog-A approach also allows the embedding of nonlinear length, width and bias effects into BSIM calculated curves beyond those that can be achieved by the use of different BSIM parameter sets. Nonlinear dependences are necessary to capture effects particular to 4 K behavior, such as current kinks. The 4 K DC behavior is reproduced well by the compact model and the model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and widths. The incorporation of various length/width and bias dependent effects into one Verilog-A/BSIM4 library, therefore, produces one model for all sets of devices called up in a given product design kit (PDK) for this technology node.     

Sensitivity and crosstalk study of the zero gap microlens used in 3.2 μm active pixel image sensors

The microlens has been widely applied to improve the sensitivity and to decrease the spatial crosstalk of image sensors. In order to further decrease the pixel size while improve the image quality, the zero gap microlens has been proposed to make high performance image sensors. In this paper, both the traditional microlens and zero gap microlens are fabricated using TOWER and TOPPAN processes. And their performances are compared and evaluated. The results show that the least sensitivity of the zero gap microlens has been significantly improved by more than 45.8% compared to that of the traditional microlens. The use of the zero gap microlens results in an obvious decrease of the crosstalk among blue, green and red lights. For example, the crosstalk of blue light in red light under the green irradiation has been decreases about 1.33%, and the crosstalk of red light in blue light under the blue irradiation has showed about 2.429 times decrease. Overall, the output colour image of the zero gap microlens is brighter and clearer than that of the traditional microlens. Image quality has been significantly improved due to the use of the zero gap microlens.     

Dilute nitrides and 1.3 μm GaInNAs quantum well lasers on GaAs

We present epitaxial growth of GaInNAs on GaAs by molecular beam epitaxy (MBE) using analog, digital and N irradiation methods. It is possible to realize GaInNAs quantum wells (QWs) with a maximum substitutional N concentration up to 6% and a strong light emission up to 1.71 μm at 300 K. High quality 1.3 μm GaInNAs multiple QW edge emitting laser diodes have been demonstrated. The threshold current density (for a cavity of 100×1000 μm²) is 300, 300, 400 and 940 A/cm² for single, double, triple and quadruple QW lasers, respectively. The maximum 3 dB bandwidth reaches 17 GHz and high-speed transmission at 10 Gb/s up to 110 °C under a constant voltage has been demonstrated.     

A 0.18 μm CMOS ring VCO for clock and data recovery applications

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioral simulations predict an 18% tuning range for the oscillator, with −91 dBc/Hz phase noise at 1 MHz offset. Its power consumption has been simulated to be as low as 15.3 mW and the variation of its DC level of oscillation is 20 mV, which corresponds to 1.3% of its mean value. While consuming less area than an LC VCO, the proposed oscillator design achieves a more stable and reliable operation point.     

Design of a 30 GHz rotary traveling wave oscillator with improved frequency tuning range in 0.18 μm CMOS technology

In this paper, the operation of rotary traveling wave oscillators is analyzed, the general oscillation condition is derived, and analytical formula for the oscillator loss is presented. Based on this analysis, switched transmission line is employed to extend the output frequency tuning range. Post-layout simulation shows a frequency tuning range of 3.1 GHz in the vicinity of 30 GHz. The proposed half-quadrature VCO exhibits a phase noise better than −102.2 dBc/Hz at 1 MHz offset frequency. The VCO provides an output power level ranging from −6 to −2.5 dBm with drawing 15.2 mA of dc current from a 1.8 V power supply.     

Microstructure,electric flame-off (EFO) characteristics and tensile properties of silver–lanthanum alloy wire

Silver has potential for application in the electronic packaging industry because of its great electrical and thermal properties and lower price compared to that of gold. Silver oxidizes easily, so doping lanthanum to form Ag–La alloy improves its anti-oxidation capacity. In this study, the microstructure, tensile properties, electronic flame-off (EFO) characteristics, and fusing current of Ag–La alloy wire (φ = 20 μm) are studied. Samples annealed at three temperatures (325 °C, 375 °C, and 425 °C) are analyzed. According to the experimental results, after annealing at 425 °C, Ag–La alloy wire recrystallized, giving it a tensile strength similar to that of pure silver wire and a uniform structure. Doping lanthanum reduced the diameter of free air balls (FABs) in the EFO process. The fusing current of Ag–La wire was about 0.45 A, and the grains of Ag–La wire grew to the size of the wire diameter when a 0.4 A current (90% fusing current) was applied for a long time. Ag–La alloy wire can be used in the electronic packaging industry.     

Fabrication of highly reflective gratings in 1.5 μm semiconductor lasers using focused ion beam-based etching

This paper reports on fabrication of semiconductor/air gratings in 1.5 μm double-section semiconductor lasers to achieve a high reflectivity in order to compensate low round-trip gain. Fabrication of the gratings with varying thicknesses and with thicknesses down to 160 nm is carried out at the gain section of the double-section diode laser using focused ion beam etching (FIBE) and inductively coupled plasma (ICP) techniques. Theoretical results of reflectivity are given for 1.5 μm AlGaInAs/InP semiconductor lasers by adding wavelength dependence of the refractive index into the calculations. We also compare our reflectivity results with that of a commercial simulation program and show a good agreement between them. Our results demonstrate that the gratings fabricated consist of only six air/semiconductor layer pairs and achieve theoretical reflectivity higher than 99%. Due to a high index contrast of the both layers, n_l = 1, n_h ∼ 3.5, a reflectivity bandwidth of >230 nm is obtained in 1.5 μm semiconductor lasers. Finally, lasing operation from AlGaInAs/InP semiconductor lasers with highly reflective grating section is achieved with a low threshold current of ∼8 mA, which is almost three times lower than devices without semiconductor/air gratings.     

A dual front-end for the new GPS/GALILEO generation in a 0.35 μm SiGe process

A highly integrated, low-power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 μm SiGe process. First an analysis of the current and future GPS and GALILEO signals is presented in order to show the interoperability between both systems and to set the requirements for the entire front-end. The receiver has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4.092 MHz after digitalization. The ESD protected RF front-end exhibits a voltage gain of 103 dB and an SSB noise figure of 3.7 dB, which makes it suitable for high-sensitivity applications. The achieved power consumption is only 66 mW from a 3 V voltage supply and 38 mW if the internal dual-gain LNA is switched off with no compromise with performance and with a minimal amount of external components.     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.     

Control of filament size and reduction of reset current below 10 μA in NiO resistance switching memories

Resistive-switching memory (RRAM) is receiving a growing deal of research interest as a possible solution for high-density, 3D nonvolatile memory technology. One of the main obstacle toward size reduction of the memory cell and its scaling is the typically large current I_reset needed for the reset operation. In fact, a large I_reset negatively impacts the scaling possibilities of the select diode in a cross-bar array structure. Reducing I_reset is therefore mandatory for the development of high-density RRAM arrays. This work addresses the reduction of I_reset in NiO-based RRAM by control of the filament size in 1 transistor-1 resistor (1T1R) cell devices. I_reset is demonstrated to be scalable and controllable below 10 μA. The significance of these results for the future scaling of diode-selected cross-bar arrays is finally discussed.     

A resonant half bridge driver with novel common mode rejection technique implemented in 1.0 μm high voltage (650 V) DIMOS process

In this paper, a half bridge convert driver IC with novel common mode rejection technique is designed and implemented in 1.0 μm high voltage (650 V) Dielectric Isolation MOS (DIMOS) process. The Designed IC is suitable for medium power (under 500 W) applications such as consumer electronics. Half bridge converter driver IC with a novel common mode rejection technique, which is composed of noise filter and set inhibitor, shows high dv/dt noise immunity up to 66.67 V/ns. Spectre simulation was performed to verify the electrical characteristics of the designed IC.     

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications

This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.¹