Low power current-mode binary-tree asynchronous Min/Max circuit

A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20 μA and data rate of 11 MHz the circuit dissipates 505 μW, while for the signals of 200 nA and data rate of 500 kHz the power dissipation is reduced to 1 μW. The prototype circuit with four inputs, realized in the CMOS 0.18 μm technology, occupies the area of 1800 μm².     

Hybrid asynchronous circuit generation amenable to conventional EDA flow

This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., quasi-delay insensitive (QDI)) dual-rail of asynchronous circuits. Precisely, we propose a clever way of partitioning an input (synchronous) circuit to transform it into a circuit with single-rail and dual-rail sub-circuits and of designing seamless interface to stitch the sub-circuits. Our proposed synthesis flow closely links to industrial design automation tools with standard cell libraries to enhance the practicality and productivity. Experimental results show that the designs produced by our approach expose partial or full combinations of high-performance, low-power consumption, great immunity to delay and noise variability, and mitigation to the side-channel attacks in hardware security.     

Simple method of asynchronous circuits implementation in commercial FPGAs

This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require the application of additional user actions such as constraining or building hard macros. As a design example, an architecture of the asynchronous PicoBlaze compatible microcontroller and 12-bit pipelined fast array multiplier have been considered. The developed synchronous and asynchronous versions of the microcontroller as well as fast array multiplier have been implemented and tested using Xilinx FPGAs, and then compared in terms of the area requirement, power consumption and performance.     

QNoC asynchronous router

An asynchronous router for quality-of-service Networks on Chip (QNoC) is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each SL. VCs are assigned dynamically per packet in each router. The router employs fast arbitration schemes to minimize latency. Analytical expressions for a generic NoC router performance, area and power are derived, showing linear dependence on the number of buffers and flit width. The analytical results agree with QNoC router simulation results. The QNoC router architecture and specific asynchronous circuits are presented. When simulated on a 0.18 μm process, the router throughput ranges from 1.8 to 20 Gbps for flits 8-128 bits wide.     

Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit

In this work, to increase the reliability of low power digital circuits in the presence of soft errors, the use of both III-V TFET- and III-V MOSFET-based gates is proposed. The hybridization exploits the facts that the transient currents generated by particle hits in TFET devices are smaller compared to those of the MOSFET-based devices while MOSFET-based gates are superior in terms of electrical masking of soft errors. In this approach, the circuit is basically implemented using InAs TFET devices to reduce the power and energy consumption while gates that can propagate generated soft errors are implemented using InAs MOSFET devices. The decision about replacing a subset of TFET-based gates by their corresponding MOSFET-based gates is made through a heuristic algorithm. Furthermore, by exploiting advantages of TFETs and MOSFETs, a hybrid TFET-MOSFET soft-error resilient and low power master-slave flip-flop is introduced. To assess the efficacy of the proposed approach, the proposed hybridization algorithm is applied to some sequential circuits of ISCAS’89 benchmark package. Simulation results show that the soft error rate of the TFET-MOSFET-based circuits due to particle hits are up to 90% smaller than that of the purely TFET-based circuits. Furthermore, energy and leakage power consumptions of the proposed hybrid circuits are up to 79% and 70%, respectively, smaller than those of the MOSFET-only designs.     

LCD控制器中异步电路的设计

异步电路的设计能够解决功耗、系统速度、时钟偏移等问题,成为当前VLSI研究的热点.文章提出了4级灰度LCD控制器异步电路的设计方案,通过异步控制以消除无效操作从而降低功耗,经验证平均功耗仅为同步电路的23.7%：异步电路还实现了部分显示和滚屏等功能,加快了系统响应速度.     

Statistical analysis of asynchronous pipelines in presence of process variation using formal models

Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is one of the possible interconnect platforms in multiprocessor systems on a chip. Designing proper links and buffers in these circuits can improve their performance. An asynchronous pipeline is a key element in buffer designs. The type of pipeline and its size can influence the performance metrics such as power consumption and delay. However, asynchronous pipelines face some challenges such as performance evaluation, verification, and process variation. We consider a new formal model to overcome these challenges simultaneously. In this paper, a new statistical model for asynchronous pipelines based on Generalized Stochastic Petri Net (GSPN) has been developed. This model can be applied to different pipeline stages, in order to compare them based on the statistical analysis of performance metrics (power consumption and delay), and to analyze their performance and timing verification in presence of variation. We have explored various kinds of asynchronous pipelines, and their corresponding results show this model has reasonable accuracy in average (below 5%) and in variance, compared to the low level Monte Carlo Hspice simulation.     

基于180nm COMS工艺的低功耗温度传感器电路设计

为降低温度传感器的功耗,提出一种结构简单的片上温度-频率转换器电路。该转换器能够根据与绝对温度成比例（proportional to absolute temperature, PTAT）的电流检测出温度,利用源极耦合多谐振荡器电路,将温度等效PTAT电流转换成频率。提出的电路采用标准180nm CMOS技术设计,面积约为0.061 mm2。通过多次实际测量,结果显示：当电源电压为0.8 V ±10%时,该温度传感器能够在?43 °C~+85 °C的温度范围内良好工作,并且经过单点校正之后,最大温度误差小于±1 °C。当电源电压为0.8 V时,+85 °C条件下的平均功率损耗仅为500 nW。     

低功耗三值双边沿触发器设计

提出了几种分别采用两个锁存器和单个锁存器的三值双边沿触发器设计方案，这些方案包括动态、半静态和静态结构。双锁存器三值双边沿触发器是通过将两个透明的三值闩锁并列构成的。单个锁存器的三值双边沿触发器设计是通过时钟信号的上升沿及下降沿后分别产生的窄脉冲使锁存器瞬时导通完成取样求值。三值双边沿触发器具有对时钟信号的两个跳变均敏感的特点，因此可以抑制时钟信号的冗余跳变。较之三值单边沿触发器，在保持相同数据吞吐量的条件下，采用三值双边沿触发器可使时钟信号的频率减半，从而降低系统功耗。最后给出了采用0．25μm CMOS工艺参数的HSPICE模拟结果及其功耗比较。     

异步集成电路设计的研究与进展

回顾了异步集成电路设计发展的历史,阐述了当前异步集成电路重新引起重视的原因,总结了异步集成电路的优势,并对异步集成电路设计方法进行了简要地概括,介绍了实用的异步集成电路芯片,最后分析了异步集成电路面临的挑战,并揭示了它今后的发展方向.     

Low power and high speed multiplier design with row bypassing and parallel architecture

This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18 μm CMOS technology and 1.8 V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16×16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.     

Graph-based STA for asynchronous controllers

We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant timing differences between the ASTA critical cycle and STA critical path, with cut cycles. We also demonstrate our correlation to SPICE level simulations, for 20 of the 23 circuits. Our ASTA flow effectively upper bounds critical cycle delay over SPICE, and is orders of magnitude faster.     

一个异步低功耗微控制器的结构设计与VLSI实现

介绍了一个低功耗微控制器的结构设计与VLSI电路实现。适当地选择并设计了微控制器的体系结构和流水线,同时采用了异步逻辑的电路实现方法。该微控制器与PIC16C61的指令集兼容,功能相仿。在Chartered0.6μm 的工艺条件下,平均功耗只有PIC16C61的16％。与其它各种类型的现有微控制器相比,功耗的下降更为明显。     

脉冲LD驱动电源的功率电路设计

激光二极管高性能的安全工作,离不开可靠的驱动电源。本文重点阐述了脉冲LD驱动电源的功率电路设计,包括电压型和电流型两种充电方式;储能电容的实际选择以及脉冲大电流的两种实现方式。     

低功耗双边沿触发器的逻辑设计

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能,能够正常地应用于时序电路的设计,并且由于时钟工作频率减半而导致系统功耗的明显降低．     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

一种变波特率异步串口通信电路设计

计算机串口最大波特率为115.2 kbit/s,高于计算机最大波特率工作的设备不能直接用计算机进行调试或测试.提出一种基于TMS320C2812和XR16C2852芯片实现的两路波特率不同的异步串口通信电路设计方案,为高于计算机串口波特率115.2 kbit/s的被测/调试设备提供与计算机在线串口调试或测试平台.     

High speed sample and hold design using closed-loop pole-zero cancelation

A new closed loop Sample-and-Hold (S&H) architecture is proposed for pipeline analog-to-digital converter (ADC) that breaks the precision-speed-power trade off by means of canceling out the first closed loop pole. This pole-canceling results in widening the bandwidth of the S&H up to the second pole. In this architecture, two amplifiers are used: one for accuracy with little power consumption, another one for high-speed response, which consumes most of the total power. Exploiting these two amplifiers remedies some of the tradeoffs and limitations of opamp design in S&H circuits. Simulated by HSPICE with a standard BSIM3v3 0.13 μm technology, the S&H achieves 80 dB SFDR for a 1.6 V_ppd output at 500 MHz sampling rate.     

引信电源性能测量电路设计

介绍了一种存储测试系统,该系统可以对处于高冲击和高速旋转恶劣环境中的引信电源的一些重要参数进行测量。电路采用单片机和CPLD联合控制的方法,充分利用了CPLD的高速和MCU控制灵活的特点,实现了数据采集和Flash存储器的读、写、擦除操作,以及与上位机通信的控制,从而实现微体积、微功耗、大容量的存储测试系统设计。分析了在闪存中构造负延迟存储空间的方法,以及AD校准的方法。整个系统经过实测在恶劣的环境中能够稳定的工作,达到了设计的目的,系统同样可以用于测试一般的化学电池。     

大功率数码管驱动电路的优化设计

对大功率数码管（LED）的功耗进行了分析和计算,指出大功率LED不能简单地用七段译码器进行驱动,而必须进行专门设计。以5英寸数码管为例,对其译码驱动电路进行了对比研究,指出在各种驱动电路中,基于数字芯片MC1413的驱动电路是最优设计。设计了实验电路,实验结果验证了理论分析的正确性和所提出方法的可行性。