A new successive approximation architecture for high-speed low-power ADCs

A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40 Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture.     

A high-speed, low-power clock generator for a microprocessorapplication

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 μm process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than ±100 ps     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.     

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range. Wing Foon Lee was born in Singapore. He had worked as an application engineer for more than two years. He received his B.Eng., M.Eng. and Ph.D. degrees in Electrical & Electronic Engineering from Nanyang Technological University, Singapore in 1996, 1999 and 2005 respectively. His research interest is on low power analog circuit design, high precision readout circuits and signal-conditioning circuits for sensor applications. P. K. Chan was born in Hong Kong. He received the B.Sc. (Hons) degree from the University of Essex, Colchester, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology (U.M.I.S.T.), Manchester, U.K., in 1988, and the PhD degree from the University of Plymouth, U.K. in 1992. From 1989 to 1992, he was a Research Assistant with the University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics (IME) as a Member Technical Staff, where he designed CMOS sensor interfaces for industrial applications. In 1996, He was a Staff Engineer with Motorola, Singapore where he developed the magnetic write channel for Motorola 1st generation hard-disk preamplifier. He joined Nanyang Technological University (NTU), Singapore in 1997, where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director [analog/mixed-signal IC and applications] for the Center for Integrated Circuits and Systems (CICS). He holds four patents and is an IC Design Consultant to local and multi-national companies in Singapore. He has also conducted numerous IC design short courses to the industrial companies and design centers. His research interests include circuit theory, amplifier frequency compensation techniques, sensing interfaces for integrated sensors, biomedical circuits and systems, integrated filters and data converters.     

一种用于FPGA的270MHz到1.5GHz可重构多功能锁相环时钟发生器

本文设计实现了一种用于FPGA芯片的可重构多功能的锁相环时钟发生器。该时钟发生器具有可配置的时钟发生和延时补偿两种模式,分别实现时钟倍频和相位对准的功能。输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。为了提高相位对准和相移的精度,本文设计了一种具有新的快速起振技术的压控振荡器。本文还提出了一种延时分割方法以提高用于实现相移和占空比调节功能的后端分频器的速度。整个时钟发生器使用0.13μm标准CMOS工艺设计制作。测试结果表明,能够实现270MHz到1.5GHz的宽调节范围,当锁定在1GHz时,整个电路功耗为18mW,rms抖动小于9ps,锁定时间为2μs左右。     

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.     

A low-power spread-spectrum clock generator with three-step frequency and VCO gain calibration for serial-ATA applications

This paper presents a low power ring oscillator-based spread-spectrum clock generator with three-step frequency and voltage-controlled oscillator (VCO) gain calibration for S-ATA applications. To meet the low jitter requirements with a small VCO gain, a ring-type VCO with three step frequency calibration and gain calibration scheme is proposed. The proposed coarse tuning method selects the optimal tuning currents and capacitances of the ring VCO to optimize the phase noise. The gain of ring-type VCO can be reduced and kept constant with the proposed three-step frequency and VCO gain calibration. As a result, it can improve the phase noise characteristics of the ring-type VCO and make it more robust to the PVT variations. Also, charge pump up/down current mismatches are compensated with the current mismatch compensation block. This chip is fabricated with 65 nm CMOS technology, and the die area is 430 × 460 μm². The power consumption is 12 mW at 1.2 V supply voltage. The measured RMS jitter and phase noise are 2.835 ps and ?96.83 dBc/Hz at 1 MHz offset, respectively.     

一种用于抑制EMI的单片数字式随机载波扩频时钟产生器

本文提出一种全集成的随机载波频率调制扩频时钟产生器,抽象出了它的解析模型并且仿真和讨论了调制参数对扩频效果的影响。该扩频时钟信号产生器利用数字化可变电流调制技术,通过直接改变时钟信号产生器中振荡电容的充/放电电流的大小来改变时钟信号产生电路输出时钟信号频率,产生扩频时钟信号。本电路避免使用难以集成的滤波器件,从而降低了芯片的面积;而用数字技术来产生扩频时钟信号具有较低的功耗和良好的鲁棒性。本文中的RCF-SSCG已经在0.5µm CMOS工艺下制造出来并用于Class D放大器,占用面积 0.112 mm2 ,功耗为9mW。实验结果验证了理论分析。     

An advanced monolithic digitalized random carrier frequency spread-spectrum clock generator for EMI suppression

A novel monolithic digitalized random carder frequency modulation spread-spectrum clock generator (RCF-SSCG) is proposed. In this design, the output frequency of the proposed RCF-SSCG changes with the inten-sity of the capacitive charge and discharge current. Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed. Compared with other works, this design has the advantages of small size, low power consumption and good robustness. The circuit has been fabricated in a 0.5 μmCMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm2and consumes 9 mW. The experimental results confirm the theoretical analyses.     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.     

一种应用于超宽带（UWB）的CMOS五次微分高斯脉冲发生器

A CMOS fifth-derivative Gaussian pulse generator is presented for ultra-wideband （UWB） applications. The design exhibits low power consumption, low circuit complexity, and a precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The pulse generator is implemented with a 1.8-V, 0.18-μm CMOS process. The small core chip size of the pulse generator is only 217 ×121 #m2 because of its all digital circuit design. The measured fifth-derivative Gaussian pulse has a peak-to-peak amplitude of 158 mV and a pulse width of 800 ps. The average power dissipation is 0.6 mW with a pulse repetition frequency of 50 MHz.     

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65 nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07 mm². The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60 dB, a spurious free dynamic range of 73.35 dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85 mW at a 1.1 V supply and achieves a figure-of-merit of 51 fJ/conversion-step.