Doping compensation for increased robustness of fast recovery silicon diodes

High-power diodes with the radiation enhanced diffusion (RED) of Pd are shown to have much higher ruggedness during the reverse recovery compared to that of the Pt. Anode doping profiles measured by spreading resistance technique after a 10 MeV He implantation with subsequent annealing between 500 and 800 °C reveal different compensation effects between the Pd and Pt. The in-diffusing Pd converts the n-type background doping concentration of N_D = 3 × 10¹³ cm⁻³ in the position of radiation defects to that of a p-type with about one order higher concentration. The created low-doped p-layer significantly increases ruggedness of diodes during reverse recovery. In the diodes with the Pt layer, only a modest compensation is observed, a conversion to a p-type layer is missing and robustness is much lower. The DLTS spectra for the Pt and Pd devices show a similar electronic structure and introduction rates of defects at 700 °C, while they differ significantly at 600 and 650 °C both for the majority and minority carriers. It is preliminary suggested that the strong compensation effect after the RED of Pd is caused by a high introduction rate of an acceptor deep level at the lower half of the silicon bandgap.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi

It is reported that the thermal stability of NiSi is improved by employing respectively the addition of a thin interlayer metal (W, Pt, Mo, Zr) within the nickel film. The results show that after rapid thermal annealing (RTA) at temperatures ranging from 650 °C to 800 °C, the sheet resistance of formed ternary silicide Ni(M)Si was less than 3 Ω/□, and its value is also lower than that of pure nickel monosilicide. X-ray diffraction (XRD) and raman spectra results both reveal that only the Ni(M)Si phase exists in these samples, but the high resistance NiSi₂ phase does not. Fabricated Ni(M)Si/Si Schottky barrier devices displayed good I-V electrical characteristics, with the barrier height being located generally between 0.65 eV and 0.71 eV, and the reverse breakdown voltage exceeding to 40 V. It shows that four kinds of Ni(M)Si film can be considered as the satisfactory local connection and contact material.     

Buried-Pt gate InP/In0.52Al0.48As/In0.7Ga0.3As pseudomorphic HEMTs

InP-based high electron mobility transistors (HEMTs) were fabricated by depositing Pt-based multilayer metallization on top of a 6-nm-thick InP etch stop layer and then applying a post-annealing process. The performances of the fabricated 55-nm-gate HEMTs before and after the post-annealing were characterized and were compared to investigate the effect of the penetration of Pt through the very thin InP etch stop layer. After annealing at 250 °C for 5 min, the extrinsic transconductance (G_m) was increased from 1.05 to 1.17 S/mm and Schottky barrier height was increased from 0.63 to 0.66 eV. The unity current gain cutoff frequency (f_T) was increased from 351 to 408 GHz, and the maximum oscillation frequency (f_max) was increased from 225 to 260 GHz. These performance improvements can be attributed to penetration of the Pt through the 6-nm thick InP layer, and making contact on the InAlAs layer. The STEM image of the annealed device clearly shows that the Pt atoms contacted the InAlAs layer after penetrating through the InP layer.     

Direct observation of ICT cations at the HTL/transparent semiconductor interface

The cation density at the interface of a transparent anode and an organic layer has been measured for several hole transport (HT) materials. The number of cations at the interface of ITO:MoO_x with rubrene, NPB, m-MTDATA and TCTA was found to range from 8 × 10¹³ to 1.5 × 10¹⁴ per cm² in freshly prepared devices. These values decreased by about 25% after one month. These cations are part of the dipole layer that results from the transfer of electrons from an organic layer, whose adiabatic ionization potential is less than the work function of the anode.     

Characterization of strained silicon on relaxed SiGe layer made by H ion implantation and annealing in ultra-high vacuum ambient

Twenty-nanometer-thick Si cap layer/74-nm-thick Si_0.72Ge_0.28 epilayer/Si heterostructural sample was implanted by 25 keV H⁺ ion to a dose of 1 × 10¹⁶ cm⁻² and subsequently annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristic of Si/SiGe/Si heterostructure. Investigations by RBS/C demonstrate that the Si_0.72Ge_0.28 layer show good crystal quality (21.1% of channel minimum yield). The relaxation degree of partially relaxed Si_0.72Ge_0.28 layer was around 74%, which was obtained by HRXRD. The computation process of the relaxation degree of strain in SiGe layer according to HRXRD rocking curve was also thoroughly introduced. Raman analysis revealed that stress, σ and strain, ε in the thin strained-Si layer were around 1.2 Gpa and 0.52%, respectively. In addition, the small surface roughness in the formed strained-Si/relaxed Si_0.72Ge_0.28 layer/Si heterostructural sample was observed via AFM image.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Vacuum-free lamination of low work function cathode for efficient solution-processed organic light-emitting diodes

The low work function cathode of blade-coated organic light-emitting diode is transferred from a soft polydimethylsiloxane (PDMS) mold by lamination without vacuum. The cathode is a bilayer of polyethylene glycol (PEG) (<10 nm) and Al (100 nm). A sacrificial layer of polystyrene with low Mw 1500 and melting point of 120 °C is inserted between the cathode and PDMS for the subsequent mold removal at 150 °C by melting polystyrene. Current efficiency of 3 cd/A (1.1%) and luminance of 2500 cd/m² are achieved for green polyfluorene fluorescent emitter. 25 cd/A (8.2%) and 3200 cd/m² are achieved for green phosphorescent tris[2-(p-tolyl)pyridine]iridium(III) (Ir(mppy)₃) emitter in polymer blend host. The efficiency is about 70% of the devices with thermally evaporated cathode. The turn-on voltage is about 5 V higher.     

Electrical properties and interfacial chemical environments of in situ atomic layer deposited Al2O3 on freshly molecular beam epitaxy grown GaAs

Interfacial chemical analyses and electrical characterization of in situ atomic layer deposited (ALD) Al₂O₃ on freshly molecular beam epitaxy (MBE) grown n- and p- GaAs (001) with a (4 × 6) surface reconstruction are performed. The capacitance-voltage (C-V) characteristics of as-deposited and 550 °C N₂ annealed samples are correlated with their corresponding X-ray photoelectron spectroscopy (XPS) interfacial analyses. The chemical bonding for the as-deposited ALD-Al₂O₃/n- and p-GaAs interface is similar, consisting of Ga₂O (Ga¹⁺) and As-As bonding (As⁰) without any detectable arsenic oxides or Ga₂O₃; the interfacial chemical environments remained unchanged after 550 °C N₂ annealing for 1hr. Both as-deposited and annealed p-GaAs metal-oxide-semiconductor capacitors (MOSCAPs) exhibit C-V characteristics with small frequency dispersion (<5%). In comparison, n-GaAs MOSCAPs shows much pronounced frequency dispersion than their p-counterparts.     

Effects of surface treatment of ITO anode layer patterned with shadow mask technology on characteristics of organic light-emitting diodes

We investigated the effects of various surface treatments of indium tin oxide (ITO) on the electrical and optical characteristics of organic light-emitting diodes (OLEDs). A 150-nm-thick ITO anode layer was patterned directly with a shadow mask during the sputtering process without the use of a conventional photolithography patterning method. The sputtered ITO layer was subjected to thermal and oxygen plasma treatments to reduce the sheet resistance and improve surface roughness. The thermal treatment was performed for 1 h at temperatures of 250 and 380 °C, which were chosen so that the glass substrates would not deform from thermal damage. The measured sheet resistance decreased from 30.86 Ω/sq for the as-sputtered samples to 8.76 Ω/sq for the samples thermally treated at 380 °C for 1 h followed by oxygen plasma treatment. The root-mean-square surface roughness measured by atomic force microscopy considerably decreased to 3.88 nm with oxygen plasma treatment. The thermal treatment considerably decreased the sheet resistance of the ITO anode layer patterned with the shadow mask. The spike-like structures that are often formed and observed in shadow mask-patterned ITO anode layers were almost all removed by the oxygen plasma treatment. Therefore, a smooth surface for shadow mask-patterned ITO layers with low sheet resistance can be obtained by combining thermal and oxygen plasma treatments. A smooth surface and low sheet resistance improves the electrical and optical characteristics of OLEDs. The surface-treated ITO layer was used to fabricate and characterize green phosphorescent OLED devices. The typical characteristics of OLED devices based on surface-treated shadow mask-patterned ITO layers were compared with those fabricated on untreated and photolithography-patterned ITO layers to investigate the surface treatment effects. The OLED devices fabricated by thermal treatment at 380 °C for 1 h followed by oxygen plasma treatment for 180 s showed the highest luminance and current density. Furthermore, the leakage current that might be induced by the rough ITO surface was dramatically reduced to 0.112 mA/cm². Our study showed that the shadow mask-patterned ITO anode layer treated by heat and plasma and having a low sheet resistance and surface roughness yielded excellent electrical and optical properties for OLEDs compared to those based on an untreated ITO layer. The fabricated OLED devices using the surface-treated shadow mask-patterned ITO layer exhibited comparable characteristics to those obtained from a conventional photolithography-patterned ITO anode.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Structure and property of magnetron sputtered ternary cobalt-nickel silicide films

Ternary cobalt-nickel silicide films were prepared using magnetron sputtering from an equiatomic cobalt-nickel alloy target on Si substrate. The effect of post-deposition annealing on the phase formation, structural properties and resistivity of the resultant films has been studied. The results of XRD show that the annealing temperature and impurity level of oxygen play a crucial role in controlling the phase transformation of ternary silicide. Silicide phases are absent in the as-deposited film due to the amorphous nature. At relatively low annealing temperature, the phase of CoNi₃Si (2 2 0) and CoNiSi (2 2 0) coexist. With the increase of annealing temperature, the phase of CoNi₃Si (2 2 0) begins to transform into CoNiSi (2 2 0). At high annealing temperature (800 °C), only the phase of CoNiSi₂ (2 2 2) is formed. For Co-Ni silicide film annealed in pure argon gas ambient, two Raman peaks at 1357 cm⁻¹ and 1591 cm⁻¹ are attributed to the vibrational mode of CoSi₂ and NiSi₂ compounds. For ternary silicide annealed in atmosphere ambient, two Raman peaks located at 538 cm⁻¹ and 690 cm⁻¹ were observed and may be related to Si oxide or Co-Ni oxide. The 3D views of AFM images show that the surface roughness is relatively low when the silicidation temperature is smaller than 550 °C. After silicidation in 800 °C, the surface roughness increases abruptly. The resistance initially decreases with the increase of annealing temperature, and achieves minimum value (19 μΩ cm) in temperature ranges 500-550 °C. When the annealing temperature increases from 600 °C to 800 °C, the resistivity was found to increase slightly to 26 μΩ cm. The ternary silicide shows a temperature window for low resistivity as compared to binary NiSi.     

RTD characteristics for micro-thermal sensors

The physical and electrical characteristics of MgO (medium layer) and Pt (sensor material) thin films deposited by a reactive RF sputtering method and a magnetron sputtering method, respectively, were analyzed as a function of the annealing temperature and time by using a four-point probe, SEM, and XRD. After being annealed at 1000 °C for 2 h, the MgO layer showed good adhesive properties on both layers (Pt and SiO₂ layers) without any chemical reactions, and the surface resistivity and the resistivity of the Pt thin film were 0.1288 Ω/□ and 12.88 μΩ cm, respectively. Pt resistance patterns were made on MgO/SiO₂/Si substrates by the lift-off method, and Pt resistance thermometer devices (RTDs) for micro-thermal sensor applications were fabricated by using Pt-wire, Pt-paste, and spin-on-glass (SOG). From the Pt RTD samples having a Pt thin film thickness of 1.0 μm, we obtained a temperature coefficient of resistor (TCR) value of 3927 ppm/°C, which is close to the Pt bulk value, and the ratio variation of the resistance value was highly linear in the temperature range of 25-400 °C.     

Microstructure and electric property of MgO/Fe/MgO tri-layer films forming a nano-granular system

For tunneling magnetoresistance (TMR) devices using ferromagnetic nano particle films, the size, dispersion and number of nano particles are important factors. Relating to this, single layered Fe films (thickness: t = 0.5 - 10.0 nm) sandwiched between two MgO (2 nm thick) layers were fabricated by molecular beam epitaxy. By depositing at T_s = RT (room temperature), the Fe layer had an isolated island structure for less than 1 nm thick. Correspondingly, the negative magnetoresistance effect was observed, which is characteristic of TMR. By increasing T_s, the resistivity and the magnetoresistance (MR) ratio was increased. In this study, it was found that the optimal parameters for the growth of nano particle MgO/Fe/MgO based films are t = 0.5 - 1.0 nm and T_s = RT − 120 °C.     

The microwave properties of Li doped 0.7(Ba,Sr)TiO3-0.3MgO thick film interdigital capacitors on the alumina substrates

The crystalline and electrical properties of Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick film interdigital capacitors have been investigated. Screen printing method was employed to fabricate Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick films on the alumina substrates. (Ba,Sr)TiO₃ materials have high dielectric permittivity (>500 @ 1 MHz) and low loss tangent (0.01 @ 1 MHz) in the epitaxial thin film form. To improve dielectric properties and reduce sintering temperature, MgO and Li were added, respectively. 10 μm thick films were screen printed on the alumina substrates and then interdigital capacitors with seven fingers of 200 μm finger gap were patterned with Ag electrode. Current-voltage characteristics were analyzed with elevated temperature range. Up to 50 °C, the thick films showed positive temperature coefficient of resistivity (dρ/dT) of 6.11 × 10⁸ Ω cm/°C, then film showed negative temperature coefficient of resistivity (dρ/dT) of −1.74 × 10⁸ Ω cm/°C. From the microwave measurement, the relative dielectric permittivity of Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick films interdigital capacitors were between 313 at 1 GHz and 265 at 7 GHz.     

ITO-free flexible organic light-emitting diode using ZnS/Ag/MoO3 anode incorporating a quasi-perfect Ag thin film

The multi-layer electrode (ZnS/Ag/MoO₃) was optimized by investigating the formation of a continuous Ag thin film according to the base layer. The aggregation of the Ag atom was strictly limited on the ZnS layer, which showed the best thermal stability for Ag. The thermally evaporated 7-nm-thick Ag film with surface coverage of 99.6% was achieved on the ZnS layer. We fabricated the ZnS (25 nm)/Ag (7 nm)/MoO₃ (5 nm) (Z25A7M5) multi-layer electrode, optimized through the numerical calculation. The transmittance of 83% at λ = 550 nm and sheet resistance of 9.6 Ohm/sq were recorded from the Z25A7M5 electrode. These results were mainly attributed to the uniform film-like morphology of the Ag thin film. The flexible OLEDs, based on the Z25A7M5 anode also showed feasible I–V–L characteristics compared to those of ITO-based devices.     

A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300 mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10 nm reacts with Si substrate and forms TaSi₂ at 650 °C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90 nm contacts. Top-view SEM observation on the samples after 420 °C sintering demonstrates that the Cu diffusion barrier is effective. I_on-I_off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi₂/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.     

Improvement of the field emission characteristics of an oxidized porous polysilicon using annealed Pt/Ti surface emitter electrode

The field emission characteristics of an oxidized porous polysilicon were investigated with different annealing temperatures. Pt/Ti, Ir, and Au/NiCr were used as surface emitter electrodes, and Pt/Ti emitter showed highly efficient and stable electron emission characteristic compared with the conventional Au/NiCr electrode. Thin Ti layer played an important role in promotion of adhesion of Pt to SiO₂ surface and uniform distribution of electric field on the OPPS surface. Additionally, the Ti layer efficiently blocked the diffusion of emitter metal, which resulted in more reliable emission characteristics. Pt/Ti emitter annealed at 350 °C/1 h showed the highest efficiency of 3.36% at V_ps=16 V, which resulted from the improvement of interfacial contact characteristics of thin emitter metal to an oxidized porous polysilicon. Annealing above 400 °C showed that Pt/Ti and Ir emitter electrode were thermally more stable than Au/NiCr emitter.