Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

一种应用于GPS接收机的全单片CMOS低噪声放大器

采用0.18μm1.8V mixed CMOS工艺设计并实现了一种应用于GPS接收机的CMOS低噪声放大器,采用片内螺旋电感实现输入匹配和单片集成。测试结果表明在1.575GHz时,工作电流8mA,增益20dB,噪声系数小于1.7dB,IIP3为-10dBm。     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.     

A process-tolerant out-of-band blocker rejection technique for SAW-less receivers

In this paper, an active filtering technique is presented which is capable of filtering the out-of-band blockers in wireless receivers. The concept is based on the feedforward cancellation technique where a blocker replica is subtracted at the output of the low-noise amplifier (LNA). In contrast to the previously reported feedforward cancellation methods, exact gain and phase matching are easily obtained in the proposed architecture to produce a highly selective narrowband frequency response at the output of the LNA with wide rejection bandwidth. For the proof of concept, the system is implemented in a 65 nm CMOS technology. It occupies a total area of 0.8 mm² and the current consumption is 24 mA from a 1.2 V supply. The system post-layout simulations showed a blocker rejection of more than 33 dB for blocker signals 100 MHz away from the desired signal when the feedforward path is activated. The noise figure (NF) of the entire system is 3.8 dB that degrades to 5.8 dB when the feedforward path is activated.     

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S₁₁ of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.     

Low-power current-reused RF front-end based on optimized transformers topology

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC current. Measurements of performance show a conversion gain of 28.5 dB, noise figure of 6.6 dB, 1 dB compression point of −32.8 dBm and IIP3 of −23.3 dBm at a 250 kHz intermediate frequency, while dissipating 1.45 mA from a 1.2 V supply.     

CMOS Micromachined Inductors With Structure Supports for RF Mixer Matching Networks

This letter presents the comparison of three novel structure supports for on-chip complementary metal–oxide–semiconductor (CMOS)-based micromachined inductors by using a proposed two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established and calibrated with inductor fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and the mechanical stability. The mixers, with and without micromachined process inductors, are fabricated in a 0.5-$muhbox{m}$ CMOS process and compared in this letter. The measurement results show a 28.12% increase in conversion gain, a 31.7% improvement in third intercept point, and a 44% reduction in the noise figure.