Design for Testability of CMOS Analog Sum-Product Error-Control Decoders

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation.     

Making complex mixed-signal telecommunication integrated circuitstestable

This article presents a discussion of several methods that can be used to improve the testability of complex mixed-signal telecommunication integrated circuits. We begin by outlining the role of test and its impact on product cost and quality. A brief look at the pending test crises for mixed-signal circuits is also considered. Subsequently, we outline the evolution of test strategies with time, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The article also describes several circuit techniques for improving test access and providing built-in self-test solutions for telecommunication circuits     

Event-driven Simulation and modeling of phase noise of an RF oscillator

A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.     

An architecture for a configurable mixed-signal device

The mixed-signal programmable system-on-chip (PSOC) architecture for high-volume low-cost applications is presented. Programmable analog, digital, and clocking circuits are combined with flash memory and a microcontroller to provide a platform for single-chip solutions for low-cost consumer applications. Both programmable analog and digital circuits are designed to support a moderate level of abstraction, balancing flexibility against cost and performance. A rough comparison of alternative approaches based on functionality and cost is presented.     

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-$muhbox m$technology employs only 0.3$hbox mm^2$of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip.     

模拟电子电路虚拟实验平台的设计与实现

提出了用于模拟电子电路实验教学的虚拟实验平台，该平台可以实现模拟电子电路实验实际操作与计算机模拟分析相结合的实验教学方式，同时应用虚拟仪器技术对电路进行测试和故障查找，从而培养学生应用EDA技术设计电路系统和实际操作的能力。     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range.The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.     

Hierarchical statistical analysis of complex analog and mixed-signal systems

With increasing process parameter variations in nanometre regime, circuits and systems encounter significant performance variations and therefore statistical analysis has become increasingly important. For complex analog and mixed-signal circuits and systems, efficient yet accurate statistical analysis has been a challenge mainly due to significant simulation and modelling time. In the past years, there have been various approaches proposed for statistical analysis of analog and mixed-signal circuits. A recent work is reported to address statistical analysis for continuous-time Delta-Sigma modulators. In this article, we generalise that method and present a hierarchical method for efficient statistical analysis of complex analog and mixed-signal circuits while maintaining reasonable accuracy. At circuit level, we use the response surface modelling method to extract quadratic models of circuit-level performance parameters in terms of process parameters. Then at system level, we use behavioural models and apply the Monte-Carlo method for statistical evaluation of system performance parameters. We illustrate and validate the method on a continuous-time Delta–Sigma modulator and an analog filter.     

CMOS混合信号集成电路中的串扰效应

论述了混合信号集成电路中的串扰效应及其对电路本身的影响,重点讨论了在重掺杂衬底中数字干扰对模拟器件的影响,并给出了数字噪声注入等效电路.同时从制造工艺和设计技术方面讨论了降低串扰效应的方法.     

Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI.     

Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs

We illustrate unique examples of low-power tunable analog circuits built using independently driven nanoscale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt trigger circuit and a operational transconductance amplifier C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog and mixed-signal applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may be used for efficient, tolerant and smaller circuits with tunable characteristics.     

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of “big-D/small-A” mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal “big-D/small-A” SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.      

Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial

This paper presents an overview of design techniques for a broad range of current-mode analog integrated circuits implemented in CMOS technology at a tutorial level. Primarily, emphasis is placed on circuit configurations, first-order analysis, and approximate design equations for analog integrated circuits operating in current domain for signal computation and processing applications.     

基于IEEE 1149.1标准的可重定向片上调试方法

介绍了一种基于IEEE1149．1标准的可重定向的调试方法，详细地分析了一种嵌入式调试模块的内部结构、工作原理、实现过程以及它给处理器核带来的代价，该模块在RTL级只需较少的修改即可集成在多种微处理器核上．完成片上调试的功能。     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Characterization of Floating Gate Defects in Analog Cells

A unified approach to tackle the characterization of the floating gate defect in analog and mixed-signal circuits is introduced. An electrical level model of the defective circuit is proposed extending previous models used effectively in the digital domain. The poly-bulk, poly-well, poly-power rail and metal-poly capacitances are significant parameters in determining the behavior of the floating gate transistor. The model is used to analyze the feasibility of testing a simple analog cell with the floating gate defects through the observation of the quiescent current consumption and the dynamic behavior.