Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Feasibility study of non-conductive film (NCF) for plasma display panel (PDP) application

In this study, attempts were made to develop an electrically reliable and low cost bonding process for plasma display panels (PDPs) by using non-conductive film (NCF). The adhesive joints were constructed with Ag electrodes on a glass substrate and Au finished Cu electrodes on a flexible printed circuit (FPC). To clarify the feasibility of NCF application, all experimental results of NCF were compared with those of anisotropic conductive film (ACF) which is currently used for PDP application. The reliability of adhesive interconnections using NCF and ACF was evaluated by measuring daisy resistance during high temperature and humidity storage test (85 °C, 85% RH for 1000 h). Ag electrochemical migration, which leads to the degradation of surface insulation resistance, was also investigated by measuring insulation resistance during the storage test (1000 h at 85 °C and 85% RH). The initial resistance of NCF joints was lower than that of ACF joints due to larger contact area between Ag and Au finished Cu electrodes in the NCF joints. During the reliability test, the daisy resistances of both joints increased slightly due to Z-directional swelling of the adhesives, but NCF joints showed more stable resistance than ACF joints. In addition, upon application of high voltage of 100 V (DC current), severe degradation of insulation resistance due to the Ag migration was observed in ACF joints, whereas no remarkable decrease of insulation resistance was observed in NCF joints. Conclusively, the application of NCF to PDP interconnection process has good potential from a practical point of view.     

Contact Resistance of Flip-Chip Joints in Wearable Electronic Textiles

Flip-chip bonding to a Cu lead frame transferred to a fabric was achieved by use of a non-conducting adhesive. Average contact resistance of the flip-chip joints was evaluated on variation of the Cu and Sn thickness of Cu/Sn bumps of size 150 × 220 μm². The total thickness of the Cu/Sn bumps was fixed at 15 μm. The average contact resistance of the flip-chip joints on the fabric was 5.4–10.8 mΩ, depending on the Sn thickness of the Cu/Sn bumps; this was lower than for flip-chip joints on a rigid Si substrate (15.6–26.5 mΩ). The average contact resistance of flip-chip joints on the fabric decreased from 10.8 mΩ to 5.5 mΩ when the chip–bump configuration was changed from 15-μm-thick Sn to 7-μm-thick Cu/8-μm-thick Sn. The contact resistance of flip-chip joints bonded with the 7-μm-thick Cu/8-μm-thick Sn bumps remained below 10 mΩ for up to 750 h in the 85°C/85% relative humidity test and even decreased to below 4 mΩ in the storage test at 125°C for up to 1000 h.     

Influence of crystallographic orientation of Sn-Ag-Cu on electromigration in flip-chip joint

The influence of the crystallographic orientation of Sn-3.0 wt%Ag-0.5 wt%Cu flip-chip joints and underfill on electromigration was investigated. The current density applied in our tests was 15 kA/cm² at 160 °C. Various times to failure of the test samples show a clear dependence of the electromigration behavior on the Sn grain orientations. Different microstructural evolutions were observed in all solder bumps in correlation with the crystallographic orientations of the Sn grains after an electromigration test. The primary failure of the solder joints was caused by dissolution of the Cu electrode at the cathode interface. Rapid dissolution of the Cu electrode occurred when the c-axis of the Sn grains was parallel to the direction of electron flow. On the other hand, slight dissolution of the Cu electrode was observed when the c-axis of the Sn grains was perpendicular to the direction of electron flow. Some grain boundaries interrupt the migration of Cu and the trapped Cu atoms form new grains of intermetallic compounds at the grain boundaries. In addition, underfill inhibits serious deformation of solder bumps during current stressing.     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Particle on Bump (POB) technique for ultra-fine pitch chip on glass (COG) applications by conductive particles and adhesives

Chip on glass (COG) technology is widely used in liquid crystal display (LCD) modules for connecting driver ICs to the displays especially for middle and small size panels. The most common COG technology currently used in display applications is based on anisotropic conductive films (ACF). As the increasing demand in higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. With the reduction of bump pitch, the current ACF based COG technology is confronted with two issues: one is the increase of the chances of open circuit; the other is the increase of the chances of forming shorts. A new approach for ultra-fine pitch chip on glass (COG) bonding, named ”Particle on Bump (POB)”, is proposed in this paper. In this technique, conductive particles are planted on the top surface of bumps of a driver IC through Au–Sn intermetallic connection. The driver IC is then assembled on the glass substrate of a LCD panel with an insulated adhesive by thermal press. The new method ensures that electrical connections are established only between bumps and corresponding pads. The Au–Sn reflow process for particle planting and corresponding COG bonding process were investigated in detail. The results showed that reliable connections were formed between particles and bumps through an Au–Sn intermetallic layer and final COG interconnections thus formed performed well in reliability tests. It is concluded that the POB technique overcomes the shortcomings of current ACF technique and has good potential to provide a viable ultra-fine pitch flip chip on glass solution for display applications.     

Void formation at the interface in Sn/Cu solder joints

The effect of electroplated Cu (EPC), electroplated Sn (EPS) and Cu addition (0.7 wt.%) on the void formation at the reaction interface was investigated through the reaction of solders with Cu substrates. The voids were observed at the Cu₃Sn/EPC interface in the Sn/EPC joints after aging at 150 °C, while not at the Cu₃Sn/high purity Cu (HPC) interface in the Sn/HPC joints even after aging at 180 °C for 720 h. In the EPS/HPC joints, the voids appeared at both Cu₆Sn₅/Cu₃Sn and Cu₃Sn/HPC interfaces after long time aging at 150 °C. The formation of these voids may be induced by the impurities, which were introduced during the electroplating process. The addition of Cu could reduce the interdiffusion of Cu and Sn at the interface and retard the growth of Cu₃Sn layer. Consequently, the formation of voids was suppressed.     

Carbon nanotubes for nanoscale low temperature flip chip connections

In this work we demonstrate a new approach for ultra fine flip chip interconnections based on carbon nanotubes as a wiring material. In contrast to other works we show patterned growth of multi walled CNTs on substrates with pre-structured bond pads including a complete metallization system for electrical characterization. Furthermore, we succeeded achieving a reliable flip chip connection between CNT-covered contact pads and metal pads at temperatures lower than 200 °C. Our goal is a reversible electrical and mechanical chip assembly with CNT bumps.For bonding experiments and electrical characterization a test structure with a damascene metallization including a layer stack of TiN/Cu/TiN was prepared. For CNT growth a thin nickel catalyst layer was selectively deposited with sputtering and a lift-off technique on the contact pads. The CNTs were grown by thermal CVD with ethylene as carbon source. CNT growth parameters like catalyst thickness, gas composition, growth time and temperature were optimized to get dense CNT growth. The metal bumps of the counter chip consist of electroless deposited Ni. With the selected layout we can obtain daisy chain and four-point measurements for lossless determination of single contact resistance. We have obtained reliable electrical contacts with relatively small resistance reaching values as low as 2.2 Ω. As CNT-quality is strongly dependent on the growth temperature we observed a strong change in resistivity of the flip chip connection as the growth temperature was varied. Reliability tests showed long time stability under thermal stress proving a reliable electrical contact between the contact pads. There is an appropriate potential for further optimization of the CNT bump resistance and applying this technology for IC-devices.     

Impact of board and component metallizations on microstructure and reliability of lead-free solder joints

Aging and accelerated thermal cycling (ATC) have been performed on 2512 chip resistors assembled with Sn3.8Ag0.7Cu (wt.%) solder. The boards were finished with immersion Ag (IAg), electroless nickel/immersion gold (ENIG), and hot air solder leveling Sn–Pb eutectic solder (HASL), and the components’ terminations were finished with 100% Sn and Sn8.0Pb (wt.%). The boards were reflowed with an average cooling rate of 1.6 °C/s. It was found that the microstructure and reliability of the solder joints depended on the board surface finish. The boards containing small amounts of Pb (from board/component terminations) were the most reliable. Solder joints to copper showed a significantly higher number of cycles to first failure than the joints on nickel. Better reliability of the Sn3.8Ag0.7Cu/Cu joints was attributed to an increased copper content in the bulk due to substrate dissolution.     

Microstructure and shear strength of Sn37Pb/Cu solder joints subjected to isothermal aging

The effects of isothermal aging on the microstructure and shear strength of Sn37Pb/Cu solder joints were investigated. Single-lap shear solder joints of eutectic Sn37Pb solder were aged for 1–10 days at 120 °C and 170 °C, respectively, and then loaded to failure in shear with a constant loading speed of 5 × 10⁻³ mm/s. The growth of the interfacial Cu–Sn intermetallic compounds (IMC) layer (Cu₆Sn₅ + Cu₃Sn) of Sn37Pb/Cu solder joints subjected to isothermal aging exhibited a linear function of the square root of aging time, indicating that the formation of Cu–Sn IMC was mainly controlled by the diffusion mechanism. And the diffusion coefficient (D) values of IMC layer were 1.07 × 10⁻¹⁷ and 3.72 × 10⁻¹⁷ m²/s for aged solder joints at 120 °C and 170 °C, respectively. Shear tests results revealed that as-reflowed solder joint had better shear strength than the aged solder joints and the shear strength of all aged solder joints decreased with increasing aging time. The presence of elongated dimple-like structures on the fracture surfaces of these as-reflowed or aged for short time solder joints were indicative of a ductile failure mode. As aging time further increased, the solder joints fractured in the mixed solder/IMC mode at the solder/IMC interface.     

Reliability and failure analysis of fine copper wire bonds encapsulated with commercial epoxy molding compound

The small outline transistor (SOT) devices which were interconnected with 20 μm copper bonding wire and encapsulated with commercial epoxy molding compound (EMC) have been used in a series of reliability tests which including the thermal shock test, the electrical service life test, and the isothermal aging test. Isolated IMC spots were found at the bonding interface during the thermal shock test. No void or crack was observed even after 1500 cycles thermal shock test. No electrical failure was happened. The isolated IMC spots also occurred at the Cu/Al bonds interface after 500 h electrical operation. After 1000 h electrical operation, the sizes of the IMC spots were about 0.5 μm. No layered IMC was observed. The IMCs were formed at the bonding interface when the aging temperature was between 150 °C and 250 °C. Micro cracks and Kirkendall voids were observed with the aging time of 9 days at 200 °C and the aging time of 9 h at 250 °C. The minor element in the EMC, Sb, has reacted with Cu wire and Cu bond surface at 250 °C when the aging time was more than 16 h. Cu₃Sb was the main product of the diffusion reaction. With the aging time of more than 49 h, the Cu wire was crashed into pieces and the Cu bond periphery has been severely corroded.     

Joint reliability evaluation of thermo-compression bonded FPCB/RPCB joints under high temperature storage test

In this study, electrodes on a flexible printed circuit board (FPCB) and rigid printed circuit board (RPCB) were bonded by a thermo-compression bonding. Pb-free Sn–3.0Ag–0.5Cu solder was used as an interlayer. In order to determine the optimum bonding conditions for bonding pressure and time, a 90° peel test of the FPCB–RPCB joint was conducted. The relationships between the bonding conditions, interfacial reactions, and peel strength were investigated. The optimum bonding pressure and time were 2.04 MPa and 5 s at 260 °C, respectively. Thin and uniform (Ni,Cu)₃Sn₄ intermetallic compound (IMC) layers formed at both FPCB/Sn–3.0Ag–0.5Cu/RPCB interfaces. In a high temperature storage (HTS) test of 125 °C, the peel strength decreased as the aging time increased. After the HTS test, brittle interfaces formed in the PCB joints, resulting in the switching of the failure mode from a polyimide–electrode failure to a brittle IMC failure.     

Microstructure,shear strength,and nanoindentation property of electroplated Sn–Bi micro-bumps

In order to investigate the microstructure and mechanical properties of small sized Sn–Bi bump, the eutectic Sn–Bi bumps with a diameter of 25 μm and a height of less than 20 μm after reflow were fabricated by electroplating and reflow. The reflow temperature of the Sn–Bi bumps was 170 °C, and the reflow times were varied from 5 to 20 min. The experimental results showed that a eutectic Sn–Bi composition was obtained by plating at a current density of 30 mA/cm² for 15 min. The average height and diameter of the bumps reflowed for 5 min were 16.1 ± 0.7 μm and 25.2 ± 0.7 μm, respectively. The microstructure of the reflowed bumps consisted of Sn- and Bi-rich phases. The thickness of the IMC of Cu₆Sn₅ increased from 1.17 to 2.25 μm with increasing reflow time from 5 to 20 min. The shear strength of the reflowed Sn–Bi bump increased with increasing reflow time, and reached approximately 11 gf at 15 and 20 min. The elastic modulus and hardness of eutectic Sn–Bi bump by nanoindentation were 53.5 and 0.43 GPa. Those of Cu₆Sn₅ were found to be 121.1 and 6.67 GPa.     

Room temperature wedge-wedge ultrasonic bonding using aluminum coated copper wire

The purpose of this work is to evaluate the feasibility of room temperature wedge-wedge bonding using commercially available copper wires, coated with aluminum. Bonding quality, reliability and aging resistance of the wire bonds have been investigated using standard wire pull tests immediately after bonding and after accelerated life tests, including temperature storage at 125 °C, 150 °C, and 200 °C for up to 2000 h. Using focused ion beam (FIB-) preparation and high resolution electron microscopy (SEM, TEM combined with EDX X-ray analysis), results of microstructure investigations of the Al-coating/Cu wire interface as well as of the bonding interconnect formed between the coated wire and the metallization on ceramic substrate will be presented. These investigations provide background information regarding the binding mechanisms and material interactions, and contribute to assess and to avoid potential reliability risks. Due to the found advantageous bond processing behavior and increased reliability properties, our results indicate that room temperature wedge-wedge bonding of coated copper wires has a remarkable application potential, for instance in medical and other high reliability as well as high power applications. It combines all known advantages of usual copper bonding like excellent contacting behavior, high reliability and favorable material price with the possibility of processing temperature damageable components and considerable improved storage capability. Therefore, room temperature bonding using coated copper wire can also reduce cycle time, manufacturing and material costs.     

Degradation of thermal interface materials for high-temperature power electronics applications

The specific thermal resistance values of several thermal interface materials (TIMs) intended to thermally enhance Cu contact pairs and their degradation under isothermal ageing at 170 °C have been investigated using Cu stack samples consisting of 10 Cu discs and 9 layers of the TIMs. The results obtained indicate that the specific thermal resistance values of the as-prepared Cu stack samples, one with conductive Ag thermal grease, one with Sn–3.5Ag solder joints and one with 25 μm thick Sn foil as TIMs are significantly lower than those of the Cu stack sample without any TIM. However, after the isothermal ageing at 170 °C for 90 days, the specific thermal resistance values of the samples with these TIMs are not substantially different from those of the sample without any TIM. Also reported in this paper is an estimation of testing errors for the specific thermal resistance values, microstructure characterization of the aged samples and effect of the degradation of these TIMs on the thermal performance of a high-temperature half bridge power switch module.     

Contact resistance and shear strength of the solder joints formed using Cu bumps capped with Sn or Ag/Sn layer

Solder joints were successfully bonded by joining Ag/Sn/Cu bumps and Ag/Sn/Cu layers at 200°C for 30 sec under 20 MPa, 40 MPa, and 80 MPa using thermo-compression bonder. The solder joints were aged at 150°C up to 1000 h. The strength of the solder joints was measured by the shear test and the contact resistance was measured using four-point probe method. The microstructure of the solder joints and the fracture modes after shear test were analyzed by scanning electron microscopy (SEM) with the energy-dispersive spectrometry (EDS). Results showed that the electrical resistance of the solder joints decreased, and the shear strength of the solder joints increased after aging treatment. The fracture modes were observed to move from the interfacial failure between solder and intermetallic compounds (IMCs) to the interfacial failure between IMCs. It was considered that the transition of fracture modes was closely related with the microstructure evolution of the solder joints, especially the transformation of IMC phases during the aging treatment.     

Golden bump for 20 micron diameter wire bond enhancement at reduced process temperature

With the rapid development of advanced microelectronic packaging technologies, research on fine-pitch wire bonding with improved reliability is driven by demands for smaller form factors and higher performance. In this study, thermosonic wire bonding process with a 20 μm wire for fine-pitch interconnection is described. To strengthen stitch bonds made in a gold-silver bonding system when the bonding temperature is as low as 150 °C, ball bumps (security bump) are placed on top of the stitch bonds. The ball-stitch bond and bump forming parameters are optimized using a design of experiment (DOE) method. A comparison of pull test results for stitch bonds with and without security bumps shows a substantial increase of the stitch pull force (PF) due to the use of security bonds. By varying the relative position of the security bumps to the stitch bonds via wedge shift offset (WSO), a WSO window ranging from 15 to 27 μm results in stitch PF higher than 7 gf, which is equivalent to an increase in average stitch PF of 118%.     

Study on low-Ag content Sn–Ag–Zn/Cu solder joints

The eutectic Sn–Ag–Cu solder is the most popular lead free solder. But reliability and cost issues limit its application. On the other hand, Sn–Ag–Zn system has many advantages comparing with Sn–Ag–Cu. In this paper, interfaces of Sn–xAg–1Zn/Cu and Sn–2Ag–xZn/Cu (x = 1, 2, 3), Sn–2Ag–2.5Zn/Cu and Sn–1.5Ag–2Zn/Cu solders joints were studied to understand effects of Ag and Zn contents. Results show that shearing strength of as-reflowed Sn–2Ag–2Zn/Cu and Sn–1.5Ag–2Zn/Cu joints is higher than other joints. Because of the strong Cu–Sn reaction and the formation of Ag₃Sn, the Sn–Ag–Zn series solder joints are not suitable for use above 150 °C temperature. After 250 °C soldering for 4 h, while the Zn content increased from 1 wt% to 2 wt%, the interfacial IMC of Sn–Ag–Zn/Cu altered from Cu₆Sn₅ to Cu₅Zn₈. The Cu₅Zn₈ interface has higher shearing strength than Cu₆Sn₅ interface. Relationships among microstructure, strength and aging condition are discussed.