Novel Ultra-Low-Power Class AB CCII+ Based on Floating-Gate Folded Cascode OTA

In this paper, a novel low-voltage ultra-low-power class AB current conveyor of the second generation based on folded cascode operational transconductance amplifier OTA with floating-gate differential pairs is presented. The main features of the proposed conveyor are design simplicity and rail-to-rail input voltage range at a low supply voltage of ±0.5 V. The proposed conveyor has a reduced power consumption of only 10 μW. Due to these features, the proposed conveyor could be successfully employed in a wide range of low-voltage low-power analog signal processing applications. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the results. As an example of application, a current-mode quadrature oscillator is designed and its functionality is proved by simulation.     

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII±) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII± utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of ±400 mV with a reduced power consumption of only 64 μW. A current-mode multifunction filter is presented as an application of the CCII±. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII±, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII± whereas the output signals are taken from the high-impedance output terminals Z+ and Z−. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the 0.18 μm CMOS technology are included to prove the results.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

Monolithic voltage conversion in low-voltage CMOS technologies

A high-to-low switching DC-DC converter that operates at input voltages up to two times as high as the maximum voltage permitted in a low-voltage CMOS technology is proposed in this paper. The proposed circuit technique is based on a cascode bridge that maintains the steady-state voltage differences among the terminals of all of the transistors within a range imposed by a specific low-voltage CMOS technology. An efficiency of 87.8% is achieved for 3.6-0.9 V conversion assuming a 0.18 μm CMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load.     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

Differential Difference Current Conveyor Using Bulk-Driven Technique for Ultra-Low-Voltage Applications

Nowadays the necessity of having low-voltage operation and low-power consumption is essential for electronic devices, particularly for portable electronics. Therefore, this paper presents a new ultra-low-voltage CMOS topology for a differential difference current conveyor (DDCC) based on the bulk-driven (BD) principle. Due to the use of the BD technique, the proposed circuit is capable of working with a low supply voltage of ±0.3 V and consumes about 18.6 μW with a wide input common-mode range. The proposed BD-DDCC is suitable for ultra-low-voltage low-power applications. As application examples, a voltage-mode multifunction biquadratic filter based on two BD-DDCCs and four grounded passive elements, and a fourth-order band-pass filter are presented. All passive elements of both applications are grounded, which is advantageous for monolithic integration. Also, the input voltage signals are applied directly to the high input impedance terminals, which is a desirable feature for voltage-mode operation. The simulations were performed with PSPICE using the TSMC 0.18 μm n-well CMOS technology to prove the functionality and attractive results of the proposed circuit.     

DXCCII-based grounded inductance simulators and filter applications

In this paper two new grounded inductance simulators based on DXCCII suitable for operation in 30 kHz-30 MHz frequency range, are presented. The proposed circuits both employ only a single dual X second-generation current conveyor (DXCCII) active device accompanied with three and four passive elements, respectively. The accuracy of the simulated inductors is verified by implementing them in some filter applications. Also, a novel multi-input single-output universal filter derived from one of the new grounded inductance simulators is simulated to demonstrate the functionality of the proposed circuit. Simulation results using AMS 0.35 μm CMOS process technology parameters are included.     

FGMOS based voltage-controlled resistor and its applications

The paper presents floating gate MOSFET (FGMOS) based low-voltage tunable resistor operating at supply voltages of ±0.75 V. The proposed circuit is then used as basic building block to develop tunable negative resistor, current-mode divider, and variable transresistance amplifier. The circuit is simple, compact, and accurate. The total power dissipation of the proposed circuit is 18.6 μW. The circuits are simulated to demonstrate the effectiveness using SPICE in 0.5-μm CMOS technology.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

A cross coupled low phase noise oscillator using an output swing enhancement technique

A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper?s argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about −125 dBc/Hz and −136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising.     

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,¹ named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 μW. PSpice simulation results using the 0.18 μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.     

Comparative study of sub-volt differential difference current conveyors

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limit their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG)^* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at ±300 mV supply voltage and 18.5 µW power consumption. The simulation results using 0.18 µm CMOS n-Well process from TSMC show the features of the proposed circuits.     

Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.     

A high-speed current conveyor based current comparator

In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

CMOS inverters based positive type second generation current conveyor

A new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance mode is presented in this letter. Against traditional design based on CCII+, the circuit is able to operate at low supply voltages and offers numerous advantages like class AB operation, large voltage and current swing, synthesis from digital inverters. Simulation results from a typical 0.35 μm CMOS process had demonstrated the circuit capability to operate at high frequency over wide voltage and wide current swings. The proposed circuit operation has been acted from measurements with the HEF4069UBP from Philips semiconductors [1].     

Low-voltage CMOS current-mode exponential circuit with 70 dB output dynamic range

The paper proposes new accurate exponential circuits, having a multitude of practical applications in analog signal processing. The original method for obtaining the exponential function is based on the utilization of new superior-order approximation functions. The accuracy of the proposed structures is excellent and the output dynamic range is strongly extended as a result of the fourth-order approximation and of the independence of implemented function on technological errors and on temperature variations (the best original proposed architecture of the exponential generator has an output dynamic range of 70 dB for an approximation error smaller than ±1 dB). The exponential circuits are designed for implementing in 0.18 µm CMOS technology, having a low-voltage operation (a minimal supply voltage of 1 V). The power consumptions of the proposed exponential circuits are smaller than 0.08 mW, for a supply voltage of 1 V. As application of the new exponential circuit, a dB-linear VGA circuit with high output dynamic range will be presented. The new computational structures have the possibility of generating any continuous mathematical function, presenting also an increased modularity and controllability and reduced design costs per implemented function.     

A new 0.35 μm CMOS electronic interface for wide range floating capacitive and grounded/floating resistive sensor applications

In this paper we propose a novel interface circuit suitable for the read-out of both wide range floating capacitive and grounded/floating resistive sensors. This solution, employing only two Operational Amplifiers (OAs) as active blocks and some passive components, is based on a square-wave oscillating circuit topology which, instead of a voltage integration typically performed by other solutions in the literature, operates a voltage differentiation. Therefore, the proposed circuit, performing an impedance-to-period (Z–T) conversion, results to be suitable as first analog front-end for both wide variation capacitive (e.g., relative humidity) and resistive (e.g., gas) sensors. Its sensitivity and dynamic range can be easily set through external passive components. Preliminary experimental measurements, which have characterized and validated this solution, have been conducted through a suitable prototype PCB fabricated with discrete commercial components. Then, the proposed interface has been also designed at transistor level, in a standard CMOS technology (AMS 0.35 um), developing a single-chip integrated circuit with low-voltage (1.8 V, single supply) low-power (about 350 μW) characteristics in a very small silicon area (lower than 0.6 mm²) which results to be suitable for sensor array configurations and portable applications. Further experimental results, achieved utilizing commercial sample resistors and capacitors to emulate sensor behavior, have shown a linear trend and a satisfactory accuracy in the evaluation of floating capacitive (in the range 10 pF–1 μF), grounded resistive (in the range 150 kΩ–1.5 MΩ) and floating resistive (in the range 10 MΩ–1 GΩ) variations, also when compared to other solutions presented in the literature. The satisfactory interface behavior has been also confirmed by the measurement of both relative humidity through the commercial sensor Honeywell HCH-1000 (capacitive) and carbon monoxide CO through the commercial air quality sensor FIGARO TGS-2600 (resistive).     

A Novel High CMRR High Input Impedance Differential Voltage-Mode KHN-Biquad Employing DO-DDCCs

In this work, a novel circuit configuration for realizing a differential voltage-mode Kerwin-Huelsman-Newcomb (KHN) biquad filter with high common-mode rejection ratio (CMRR) is presented. The proposed circuit is based on using the dual output differential difference current conveyor (DO-DDCC). The circuit uses three DO-DDCCs, two capacitors and five resistors. All the passive elements are grounded, which is important in integrated circuit implementation point of view. The differential voltage input signal is applied to high input impedance terminals, which is important in the voltage-mode operations. SPICE simulation results are included to verify the theory.     

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.