Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35 μm SiGe BiCMOS process.     

1.5V高速全摆幅BiCMOS逻辑电路的研究

分析了影响ＢｉＣＭＯＳ全摆幅输出和高速度的因素,探索了一种新的抑制ＢＪＴ过饱和和反馈网络,提出了具有高速全摆幅输出的ＢｉＣＭＯＳ逻辑单元。该单元可以工作于１．５Ｖ,并且易于多输入扩展,它特别适于ＶＬＳＩ设计。模拟结果表明,该单元实现了优于ＣＭＯＳ的全摆幅输出,且其速度高于同类ＣＭＯＳ电路１０倍以上。     

由RTD构成的MOBILE单元电路研究

对由共振隧穿二极管(RTD)构成的单双稳态转换逻辑单元(MOBILE)电路进行了详细地研究与分析,并结合实际RTD的特性用PSPICE进行了MOBILE单元电路模拟,总结和验证了MOBILE单元电路变化的三条规律,为进一步研究由RTD构成的多种复杂数字电路奠定了基础。     

EDA实现的PLD遥控解码电路

介绍了电子设计自动化EDA (ElectricalDesignAutomation)技术的基本特点 ,以红外遥控为例 ,提出了一种PLD (可编程逻辑器件 )解码电路 ,并用ispLSI10 6 0实现 ,该电路原理简单、设计方便、工作可靠 ,可用于以键盘扫描为输入方式的智能仪器中。     

一种零协议逻辑全异步流水线电路的优化设计研究

This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.     

Optimization design of a full asynchronous pipeline circuit based on null convention logic

peed asynchronous designs due to its high throughput and delay-insensitivity.     

一种基于厚膜工艺的电路版图设计

在电子线路版图设计中,通常采用印刷线路板技术。如果结合厚膜工艺技术,可以实现元器件数目繁多,电路连接复杂,且安装空间狭小的电路版图设计。通过对3种不同电路版图设计方案的理论分析,确定了惟一能满足要求的设计方案。基于外形尺寸的要求,综合考虑电路的性能和元件的封装形式,通过合理的电路分割和布局设计,验证了设计方案的合理性和可实现性。体现了厚膜工艺技术在电路版图设计中强大的优越性,使一个按常规的方法无法实现的电路版图设计问题迎刃而解。     

基于光电二极管检测电路的噪声分析与电路设计

光电二极管可以将光信号转化为电信号,它主要是通过半导体PN结的光电效应来实现这一转化步骤的.通过光电二极管对电路的噪声进行检测具有重要意义,就主要分析光电二极管对电路的噪声检测的价值,同时简单的分析相关的电路设计问题,希望所得结果能够为相关领域提供有价值的参考.     

基于遗传算法的组合逻辑电路设计的FPGA实现

基于遗传算法的组合逻辑电路的自动设计,依据给出的真值表,利用遗传算法自动生成符合要求的组合逻辑电路。由于遗传算法本身固有的并行性,采用软件实现的方法在速度上往往受到本质是串行计算的计算机制约,因此采用硬件化设计具有重要的意义。为了证明基于FPGA的遗传算法的高效性,设计了遗传算法的各个模块,实现了基于FPGA的遗传算法。     

Novel pipeline architectures based on Negative Differential Resistance devices

Devices exhibiting Negative Differential Resistance (NDR) in their I–V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.     

Ternary logic circuit design based on single electron transistors

Based on the I-V characteristics and the function of adjustable threshold voltage of a single electron transistor （SET）, we design the basic ternary logic circuits, which have been simulated by SPICE and their power and transient characteristics have been extensively analyzed. The simulation results indicate that the proposed circuits exhibit a simpler structure, smaller signal delay and lower power.     

Ternary logic circuit design based on single electron transistors

Based on the I-V characteristics and the function of adjustable threshold voltage of a single electron transistor (SET), we design the basic ternary logic circuits, which have been simulated by SPICE and their power and transient characteristics have been extensively analyzed. The simulation results indicate that the proposed circuits exhibit a simpler structure, smaller signal delay and lower power.     

基于补偿电路的SRAM读操作跟踪电路设计

在传统静态随机存储器（SRAM）读操作跟踪电路中,生产工艺和温度的偏差会直接影响到对SRAM中存储数据的正确读取。因此,在本文中,我们采用工艺拐点补偿和温度补偿的方法,设计出了新型SRAM读操作跟踪电路。所设计跟踪电路,通过在不同工艺拐点和不同温度的情况下,对时序追踪字线DBL补偿不同大小的电流,从而减小灵敏放大器输入位线电压差对工艺拐点和温度的敏感度。有效减小了工艺拐点和温度对于SRAM读操作的影响,提高了SRAM的良率。基于SMIC 40nm CMOS工艺,对上述读操作跟踪电路进行了仿真,并且分别对补偿前后进行了10000次蒙特卡罗仿真与比较,仿真结果验证了所设计电路的可靠性和有效性。     

一种基于晶体管逻辑状态的电路简化方法

本文提出了一种存储器（Memory）逻辑参数提取的电路简化新方法.该方法通过判断在输入特定激励向量时晶体管的逻辑状态是否改变来简化电路,研究表明新方法能大幅度减少电路中晶体管的数量,同时能很好地保持电路原有的功能特性和电气特性.基于此方法测得的逻辑参数有较好的精度,并大大加快了提取速度.实验结果表明该方法是有效的.     

基于可逆逻辑电路的脉冲分配器设计

可逆逻辑电路能大幅度降低能耗,越来越受到研究人员重视。运用可逆逻辑电路对传统脉冲分配器进行可逆设计,并提供了物理实现方法。首先对传统的脉冲分配器中的触发器和计数器进行可逆设计,然后将传统脉冲分配器的中的计数器进行替换,最后将可逆计数器和译码器级联,从而构建可逆脉冲分配器。仿真结果表明实现了脉冲分配器的功能。     

基于 AM-OLED 立体显示接口电路的设计

为了将PC机上的视频源在双AM-OLED微型显示器上实现立体显示,设计了立体视频显示接口电路。对该系统所采用的人眼的双目视差原理和SVGA050微显芯片立体显示功能进行研究。针对AM-OLED显示器的结构与特点,提出了双VGA接口为视频输入接口、PIC18LF2550为MCU控制芯片,双AM-OLED微型显示器的立体显示系统的电路设计方案;介绍了母版和OLED板的设计以及主控器利用IIC串行总线对各模块寄存器进行配置。介绍了立体显示功能实现的原理和配置SVGA050微显芯片的立体功能控制参数的方法。实验结果表明,通过对开发的立体显示系统进行左右格式的立体视频源播放测试,实现了视频源在双1.27cm(0.5in)、800×600分辨率SVGA050微显芯片上的立体显示。最后验证了基于AM-OLED微型显示器的立体显示接口电路设计方案的有效性。     

Analog circuit optimization system based on hybrid evolutionary algorithms

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.     

基于标准CMOS工艺制作的MOS-NDR柔性逻辑电路

本文利用0.35um标准CMOS工艺实现了一种由4个nMOSFET构成的MOS型负阻器件。这种负阻器件的I-V特性与传统的化合物材料构成的共振隧穿二极管（RTD）的特性类似,而且可以通过第三端来调制其I-V特性。基于这种MOS型负阻器件,本文实现了一种通过调节阈值电压来实现与非门（NAND）到或非门（NOR）转变的柔性逻辑电路。此种电路所用器件较少,而且由于使用标准IC的设计和工艺流程,制作工艺大大简化。     

A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metaloxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology.This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics.At the same time it can realize a modulation effect by the third terminal.Based on the MOS-NDR transistor,a flexible logic circuit is realized in this work,which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor.It turns out that MOSNDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.     

基于遗传程序设计的数字电路设计自动化研究

本文通过介绍电子设计自动化技术,演化硬件,遗传程序设计三个概念,并且从基于遗传程序设计的数字电路设计自动化研究中来还找寻三者的关系,并且分析遗传程序设计的算法思想及实现的方式,并将其运用到数字电路的自动化设计中去。