Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design.      

Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs

As MuGFETs are promising contenders for the end of the silicon Roadmap, their high-temperature behaviour needs to be addressed. In this work we investigate the variations of the subthreshold slope (SS) of double-gate devices and MuGFETs with intrinsic doping as a function of the temperature and fin width. Focus is placed on the superlinear behaviour of SS occurring above a certain temperature threshold. Numerical simulations are performed using Comsol Multiphysics^™ and a 1D analytical model is developed. The model, which includes the effect of film and gate oxide thickness, is shown to accurately fit the numerical data. A new definition for the subthreshold slope under high-temperature operation is proposed. The high-temperature subthreshold slope degradation is shown to increase with fin width.     

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates

The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS^TM by Silvaco Inc.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.     

A design methodology for low-leakage and high-performance buffer based on deviant behavior of gate leakage

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and ex- perimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction

Measurements were performed in thin film silicon on insulator (SOI) nMOSFETs and it was observed a transition region in the subthreshold slope, larger than the theoretically expected, when the back interface (silicon film/buried oxide) changes from accumulation to depletion. Also, it was observed a non-constant plateau in the subthreshold slope when the back interface is accumulated.

MEDICI numerical bidimensional simulations were performed in order to analyze this transition region. It was verified that there is a back gate voltage range where a part of the back interface is not depleted over the whole subthreshold region, depending on the front gate voltage, which influences strongly the determination of the subthreshold slope, resulting in a non-abrupt transient region.

It is proposed a method for extracting the interface trap density in gate oxide/silicon film and silicon film/buried oxide interfaces minimizing the influence of the back accumulation layer in the subthreshold slope with the back interface accumulated. This method was also applied experimentally.     

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (I_on), OFF-current (I_off), I_on/I_off ratio, subthreshold swing (SS) and ambipolar current (I_ambi) of the proposed device with drain underlap are investigated as gate length is scaled (L_GATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (I_off) and ambipolar current (I_ambi) are 9.49 × 10⁻¹⁴ A/µm and 1.95 × 10⁻¹² A/µm respectively for a gate length (L_GATE) of 36 nm and a channel length (L_Ch) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (L_GATE) is 72% of the channel length (L_Ch). The proposed architecture is suitable for low power applications.     

Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Analysis of subthreshold carrier transport for ultimate DGMOSFET

A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling.     

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.     

Temperature Effects on Hetero Structure Junctionless Tunnel FET

For the first time, we investigate the temperature effect on Al Ga As/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope(< 60 m V/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.