32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Impact of process parameters on circuit performance for the 32 nm technology node

As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.     

Microwave characterization of porous SiOCH permittivity after integration dedicated to the 32 nm node

New porous ULK materials are now required for maintaining a constant RC factor as back-end dimensions shrink for each new technology node. Porous SiOCH ULK HF characterization, dedicated to the 32 nm node, has been performed, and its complex permittivity extracted up to 8 GHz. The impact of process integration on the porous SiOCH is highlighted, by an increase of its real permittivity and unwanted losses.     

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

Low power options for 32 nm always-on SRAM architecture

The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which variability effects. Various alternatives have been experimented and the paper focuses on the 5T-Portless bit-cell. Read and write operations are operated by varying voltage conditions. Literature regarding 32 nm CMOS for Portless SRAM has been reviewed and improvements are presented. The bit-cells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bit-cell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption beneficial to always-on memories. The paper presents different existing solutions to limit the power consumption and their limitations in thin CMOS technologies. The portless bit-cell is presented as a low power architecture alternative to 6T-SRAM. A matrix test-chip is currently under fabrication in bulk CMOS 32 nm.     

Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90 nm on a 6T-SRAM cell. The target fins consist of straight structures (40 nm height and 17 nm of critical dimension) patterned on a 22 nm node with 90 nm fin pitch. The patterning stack consists of 70 nm of amorphous carbon as a hard mask with 25 nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32 nm node with 124 nm fin pitch was no longer functional for patterning fins on a 22 nm node with 90 nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17 nm of critical dimension on 90 nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.     

Impact of porous SiOCH on propagation performance measured for narrow interconnects of the 45 nm node

With the dimensions scaling down at each new technology node, introduction of porous dielectric materials is required to reduce the interconnect capacitance. Nevertheless, these materials are very prone to damage during integration, thus increasing their K-value (2.5 as deposited for the 45 nm node) in the final circuit. In order to characterize these effects, high-frequency measurements and electromagnetic simulations were carried out on specific microstrip structures. Taking into account typical circuit characteristics, time-domain extraction of delay values and crosstalk levels were then performed, enabling a precise analysis of moisture uptake effects from a performance point of view.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

Influence of temperature on the etching rate of SiO2 in CF4 + O2 plasma

The plasmochemical etching of SiO₂ in CF₄ + O₂ plasma is considered. During the experiment SiO₂ films are etched in CF₄ + O₂ plasma at temperatures of 300 and 350 K. The dependences of plasmochemical etching rates of SiO₂ on O₂ content in the feed are measured. The experimental measurements are compared with theoretical calculations. The obtained theoretical results are used to predict the real dimensions of etched trenches. It is found that decrease in temperature reduces lateral undercutting due to decreased desorption of formed SiF₄ molecules from the sidewalls.     

Influence of activated polymer on the etching rate of SiO2 in CF4 + H2 plasma

The reactive ion etching (RIE) of SiO₂ in CF₄ + H₂ plasma is considered. The influence of activated polymer on the RIE rate of SiO₂ in CF₄ + H₂ plasma is determined by extrapolation of experimentally measured kinetics of the etching rate. It is found that the increased surface coverage by CF₂ radicals suppresses the RIE rate of SiO₂ in CF₄ + H₂ plasma during the initial stages of the etching process. The formation of activated polymer becomes pronounced when adsorbed CF₂ radicals are slowly activated. The activated polymer intensifies the etching reaction and enhances the etching rate. At the same time, the activated polymer intensifies the polymerization reactions. The increased surface coverage by the polymer suppresses the RIE rate of SiO₂ in CF₄ + H₂ plasma at later stages of the etching process.     

Ionic outgassing from photoacid generators upon irradiation at 13.5 nm

Photoresist outgassing is considered a possible source of contamination of optics in extreme ultraviolet (EUV) lithography at 13.5 nm. We measured the relative proportions of ionic outgassing from 18 commercially available photoacid generators (PAG), which is a key component of chemically amplified photoresists, upon irradiation at 13.5 nm. These PAG include 17 triarylsulfonium or diaryliodonium salts, which contain or as the anion, and one PAG of molecular type. The overall outgassed ions in the range 10-200 u were counted in relative proportions. Outgassing of F⁺ is found to be dominant, and for most PAG the extent of F⁺ outgassing shows a satisfactory correlation with the ratio of F atomic photoabsorption to the overall PAG photoabsorption. Outgassed ions F⁺, CF⁺, and from PAG containing the anion and additional such as , and from those containing are identified. Triphenylsulfonium perfluoro-1-butanesulfonate is one PAG to emit the most abundant F⁺ and total ionic fragments, and a PAG of molecular type (N-hydroxy-5-norbornene-2,3-dicarboximide perfluoro-1-butanesulfonate) also emits abundantly both hydrocarbon ions and F⁺. Ionic outgassing of PAG cations includes (C₆H₅)₂S⁺ from R(C₆H₅)₂S⁺ salts and I⁺ from diaryliodonium salts. For PAG containing t-C₄H₉, significantly less F⁺ outgassing is observed; additional outgassing pathways are proposed. The pressure rise caused by PAG shows no dependence on the anion identity, but is correlated with cation photoabsorption, and ascribed to neutral aryl outgassing. Other minor outgassing species include from sulfonates; and ‘photostable’ PAH cations are identified for the first time and provide evidence of concurrent outgassing from, and polymerization of, PAG upon irradiation at 13.5 nm.     

Behaviour of CPW and TFMS lines at high temperature for RF applications in sub-45 nm nodes

Coplanar waveguide (CPW) and thin film microstrip (TFMS) lines integrating porous ultra low-k as inter-metal dielectric layers (k = 2.5) and copper as metal, are for the first time experimentally measured up to 110 GHz and under different temperature conditions, up to 200 °C. The extracted attenuation and propagation coefficients of those transmission lines are compared to simulations performed with MAGWEL software, a frequency domain 3-D Maxwell solver. Based on the characterization results some guidelines related to interconnect design are presented for future applications.     

Development of interference lithography for 22 nm node and below

An extreme ultraviolet (EUV) interference lithographic exposure tool was installed at the long undulator beamline in NewSUBARU to evaluate EUV resists for 25 nm node and below. The two-window transmission grating of 40 and 50 nm half pitch (hp) were fabricated with techniques of spattering, electron beam lithography, dry etching and wet etching. hp patterns (20 and 25 nm) of chemically amplified resist (CAR) and non-CAR were successfully replicated using the EUV interference lithographic exposure tool.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.     

Structural and electrical properties of Er-doped HfO2 and of its interface with Ge (0 0 1)

Er-doped HfO₂ thin films with Er content ranging from 0% to 15% are deposited by atomic layer deposition on native oxide free Ge(001). The crystallographic phase is investigated by X-ray diffraction and is found to depend on the Er%. The cubic fluorite structure develops on Ge for Er% as low as 4% and is stable after annealing at 400 °C in N₂. Microstrain increases with increasing the Er content within the fluorite structure. Time of flight secondary ion mass and electron energy loss spectroscopy evidence a Ge diffusion from the substrate that results in the formation of a Ge-rich interfacial region which does not present a structural discontinuity with the oxide. The diffusion of Ge is enhanced by the annealing and causes a reordering of the crystal lattice. In annealed films the interface defect density measured by low temperature conductance measurements is found to decrease with decreasing the Er content.     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

Epitaxy of BaTiO3 thin film on Si(0 0 1) using a SrTiO3 buffer layer for non-volatile memory application

In this study we report the epitaxial growth of BaTiO₃ films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO₃ layer using both MBE and PLD techniques. The BaTiO₃ films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO₃/Si template. The electrical characterizations of the BaTiO₃ films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO₃ layer is obtained using PLD method, which permits much higher oxygen pressure. The C-V curve shows a memory window of 0.75 V which thus enable BaTiO₃ possibly being applied to the non-volatile memory application.