High performance level restoration circuits

Three high performance level restoration circuits are proposed, which outperform the existing level restoration circuits with cross-coupled PMOS, in terms of power dissipation and delay. The first configuration employs a back-bias scheme in order to eliminate the stand-by leakage caused by the low-swing input. The second one adopts a bootstrapping technique, in order to restore the low-swing signal, without dc power consumption. Finally, a level restoration circuit is proposed, based on the generation of a narrow zero-pulse, for properly controlling the output PMOS device. The presented level restoration circuits can be implemented in standard CMOS technologies. By simulating the proposed circuits on a low-swing interconnect scheme, a 60% power savings have been observed over the conventional full-swing case.     

Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and optics-based interconnects exhibit promising physical properties for replacing the current Cu/low-k-based global interconnects. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance integrated circuits. The foregoing trends are studied with technology node and bandwidth density in terms of latency and power dissipation. Optical wires have the lowest latency and power consumption, whereas a CNT bundle has a lower latency than Cu. The new circuit scheme, i.e., “capacitively driven low-swing interconnect (CDLSI),” has the potential to effect a significant energy saving and latency reduction. We present an accurate analytical optimization model for the CDLSI wire scheme. In addition, we quantify and compare the delay and energy expenditure for not only the different interconnect circuit schemes but also the various future technologies, such as Cu, CNT, and optics. We find that the CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for a lower bandwidth requirement, whereas these advantages degrade for higher bandwidth requirements. Finally, we explore the impact of the CNT bundle and the CDLSI on a via blockage factor. The CNT shows a significant reduction in via blockage, whereas the CDLSI does not help to alleviate it, although the CDLSI results in a reduced number of repeaters due to the differential signaling scheme.      

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3sigma clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations.     

Study of swing potential on deep submicron on-chip interconnect

The low energy limit of signal on deep submicron on-chip interconnect is deduced from Shannon's communication theorem considering the influence of noise. Based on this energy limit, the analytic model of minimum swing potential considering transmission line effects is constructed. Applying the analytic model to interconnect in deep submicron technology nodes from 0.18 to 0.05 μm, it is shown that the swing potential with present low-swing technique such as SDVST could be reduced further by 70–95% according to the analysis of this work. Correspondingly, by using the low-swing interconnect technique with the minimum swing potential obtained in this work, the decrement of interconnect dynamic power dissipation can be further decreased by about 10–20% of their original one by using SDVST technique, and that of interconnect propagation delay, by one third. Furthermore, the maximum interconnect length is evaluated with a minimum swing potential value in interconnect design. All the results are valuable for interconnect performance optimization, such as repeater insertion in deep submicron circuits. As an application, the design of low swing potential interconnect with interface circuit is introduced.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-$mu$m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.      

CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects

This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy×delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver-receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0 V CMOS technology, for signal transmission along a wire-length of 10 mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy×delay.     

基于低摆幅策略的低功耗多端口寄存器文件设计

本文通过使用低摆幅策略和修改的与非型地址译码器设计了一种低功耗的寄存器文件。该低摆幅策略基于反馈机制并利用动态逻辑减少主动反馈引入的功耗。低摆幅策略分为读写两部分。在低摆幅写策略中,设计了一种存储单元用来支持低摆幅写入。修改后的NAND解码器,不仅功耗更低,同时面积也大幅减少。对比传统单端位线的寄存器文件,低摆幅技术在读和写部分能分别降低51.15%和34.5%的功耗。后仿结果表明在十二个端口同时工作时,低摆幅策略能够降低39.4%的功耗。     

Wave-pipelined intra-chip signaling for on-FPGA communications

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

A low-swing clock double-edge triggered flip-flop

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V_t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network     

An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.     

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exacerbated variability are the major concerns of sub threshold circuits. Furthermore, the global interconnects significantly affects the performance and power dissipation in sub threshold circuits. The obvious reason is the increased capacitance of long global interconnects which is further augmented with increase in sub threshold CMOS driver resistance. This paper explores the performance of sub threshold global interconnect with six different configurations of DG FinFET driver circuit viz. FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG. Performance analysis indicates that FinFET SG configuration exhibits 60.7, 0.8, 2.3, 37 and 40% better energy efficiency compared to TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG respectively at 225 mV supply voltage. Furthermore, the crosstalk analysis results shows that the glitch amplitude in TGSG driven interconnect and THYBRID driven interconnect is increased by 89.6 and 74% respectively compared to FinFET SG driven interconnect. This work also investigates the suitability of conventional buffer insertion technique for enhancing the performance of DG FinFET driven sub threshold global interconnects. The buffered and un-buffered interconnect shows comparable delay, PDP and EDP in sub threshold region. Furthermore, Monte Carlo analysis results indicate that spread in delay exhibited by FinFET SG driven un-buffered interconnect circuit is lesser by 25% compared to FinFET SG driven buffered circuit in sub threshold region.

     

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half     

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk     

Low-swing on-chip signaling techniques: effectiveness androbustness

This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity. In addition, several new interface circuits presenting even more energy savings and better reliability are proposed. Some of these circuits not only reduce the interconnect swing, but also use very low supply voltages so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Significant energy savings up to a factor of six have been observed     

High speed interconnect through device optimization for subthreshold FPGA

Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.     

A micropower, small input-to-output delay, high-voltage bipolar driver/demultiplexer IC

Describes a 2.6/spl times/2.6 mm bipolar driver/demultiplexer integrated circuit used to selectively switch one of six off-chip MOS devices. A carefully chosen chip architecture coupled with novel circuit techniques has reduced power consumption by more than two orders of magnitude over currently available micropower drivers that offer comparable performance. A low-voltage bipolar process (BV/SUB CEO/>20 V) that utilizes an extra deep n/SUP +/ diffusion (d-n/SUP +/) combines I/SUP 2/L and linear circuitry to achieve a micropower function (<100 /spl mu/W) with small input-to-output delay (<400 ns) and high-voltage capability (40 V max).     

彩色LCD绿色驱动芯片的原理与应用

Hi—FAS驱动技术应用于液晶平面显示驱动芯片,具备低功耗、低成本的优势。绿色驱动芯片除了运用Hi—FAS的驱动方式外,更进行了电源系统的改良,且具备了低温调节功耗的功能,并减少外部组件的需求,将比一般的Hi-FAS驱动芯片更省电省成本。在显示效果上具备了多段式温度补偿、串扰现象补偿、FRC演算法改良等方案,提供更优良的显示品质。     

Power characteristics of inductive interconnect

The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.