Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs

Dither-based digital background calibration algorithm has been used to eliminate the influence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signal’s amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100 MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56 dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more.     

A nonlinearity error calibration technique for pipelined ADCs

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.     

一款结合数字校正技术的流水线ADC设计

基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。     

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm² and dissipates 909 mW from a 1.8 V supply.     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

Systematic design of the pipelined analog-to-digital converter with radix<2

A systematic design of the pipelined analog-to-digital converter with radix<2 is described. A 50 MHz, 3.3 V, 10-bit pipelined analog-to-digital converter has been implemented in a 0.25-μm CMOS technology using radix<2 architecture. It achieves more than 54 dB signal-to-noise plus distortion ratio in Nyquist signal sampling at 3.0 V (10% lower than the 3.3 V nominal value) over −40 to +120 °C temperature range with a full-scale sinusoidal input. The IM3 of the converter, which is an important parameter for the OFDM based systems, is less than −64 dB. Non-linearity is reduced through digital self-calibration and correction. The digital calibration procedure takes less than 24 μS and can be done either on power up or intermittently. The layout area is 1.8 mm×1.2 mm. The converter consumes 100 mA out of a 3.3 V supply including the reference circuitry, analog cells, and all digital blocks at full-scale Nyquist sampling speed.     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

采用分段平移技术校正流水线A/D转换器级间增益的方法

分析了流水线A/D转换器采样电容与反馈电容之间的增益失配,探究了运放有限增益与流水线残差输出及A/D转换器输出的关系,建立了精确的系统模型。通过建立14位流水线A/D转换器Verilog-A的行为级模型,在数字域对流水线A/D转换器输出数字码进行分段平移。在第一级级间增益误差达到±0.012 5时,校正前信噪比仅为62 dB,校正后信噪比提升到85 dB。提出的校正方法可有效补偿由流水线级间增益导致的数字输出不连续和线性度下降。     

基于冗余子级的流水线ADC校准技术

提出了基于冗余子级的流水线ADC后端校准技术,采用精度较高的流水线冗余子级代替参考ADC,对流水线ADC的各个子级校准,替代了对整个ADC的校准,使校准系统无需降频同步,较好地解决了传统校准系统中主信号通路与参考ADC信号通路不同步的问题。对Matlab/Simulink中搭建的精度为16位、采样频率为10 MS/s的流水线ADC进行仿真,结果表明,当输入信号频率为4.760 5 MHz时,经过校准,流水线ADC的有效位和无杂散动态范围分别由9.37位和59.96 dB提高到15.32位和99.55 dB。进一步的FPGA硬件验证结果表明,流水线ADC的有效位和无杂散动态范围分别为12.73位和98.62 dB,初步验证了该校准算法的可行性。     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

A digital background calibration technique for time-interleavedanalog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm², and the power dissipation is 565 mW from a 5 V supply     

应用于流水线ADC的LMS自适应校准算法与FPGA实现

研究了应用于流水线模数转换器(ADC)的LMS自适应数字校准算法及其FPGA实现。该校准算法可用于校准大多数已知的误差,包括非线性运算放大器的有限增益、电容失配,以及比较器的失调等。通过Simulink软件,对一个12位160 MS/s的流水线ADC进行建模。采用LMS自适应校准算法对该流水线ADC进行校准,并将算法在Virtex-5上实现了硬件设计。实验结果表明, 输入信号频率为58.63 MHz时,流水线ADC的无杂散动态范围(SFDR)和有效位(ENOB)分别由校准前的46.31 dB和7.32位提高到校准后的82.03 dB和11.12位。     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

An efficient background calibration technique for analog-to-digital converters based on neural network

This paper introduces a background digital calibration algorithm based on neural network, which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as gain error, mismatch, offset and harmonic distortion. It enables an efficient background calibration through a simple feed forward neural network and LM gradient descent algorithm. The simulation results show that in the case of a signal input close to the Nyquist frequency, for a 14-bit 500 MS/s prototype ADC, only about 40,000 data needed, the ENOB of the ADC can be increased from 7.81 to 13.06 and the SFDR from 49.7 dB to 106.8 dB assisted by a lower speed reference ADC.     

Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation

A method of indirect background digital calibration of the dominant static nonlinearities in pipelined analog-to-digital converters (ADC) is presented. The method, called decision boundary gap estimation (DBGE), monitors the output of the ADC to estimate the size of code gaps that result at the decision boundaries of each stage. Code gaps result from such effects as capacitor mismatch, finite opamp gain, finite current source output impedance, comparator offset, and charge injection. DBGE does not require special calibration signals or additional analog hardware and can even reduce the performance requirements of the analog circuitry. The calibration is performed using the input signal and thus requires that the input signal exercise the codes in the vicinity of the decision boundaries of each stage. If it does not exercise these codes, then lack of calibration is less critical because the nonlinearities will not appear in the output signal. DBGE is simple and amenable to hardware and/or software implementations. Simulation results indicate DBGE is highly accurate, robust, and adaptive even in the presence of parameter drift and circuit noise.      

A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter

The continuous calibration of high-linearity, highspeed analog/digital converters (ADCs) can minimize system complexity by allowing a single converter to maintain its accuracy over time. This paper introduces a continuous calibration technique for pipelined and successive approximation ADCs that avoids some of the limitations of earlier designs by performing the calibration in the analog domain. The calibration is made transparent to the overall system by employing an extra stage that is calibrated outside of the main converter's operation and periodically substituted for a stage within the main converter. A 12-b, pipelined ADC employing this architecture has been integrated in a 0.5-μm, single-poly, quadruple-metal, 3.3-V CMOS technology. The measured dynamic performance indicates that at a 10-MHz sampling rate, the circuit achieves a peak signal-to-noise-plus-distortion ratio of 67 dB and a total harmonic distortion of -77 dR for a 4.8-MHz input. The total power dissipated by the prototype is 335 mW, and its active area is 3.71×3.91 mm²