High performance quadruple sub-harmonic mixer for millimeter-wave applications

In this paper, we present high performance quadruple sub-harmonic mixers for millimeter-wave applications. The sub-harmonic mixer was designed by using 0.1 μm GaAs PHEMT's and the coplanar wave-guide library. We show the low conversion loss of 5.8 dB at a local oscillator (LO) power of 13 dBm from the fabricated sub-harmonic mixers. The V-band sub-harmonic mixer also ensure a high degree of isolation showing −75.0 dB in the LO-to-IF and −48.1 dB in the LO-to-RF at a frequency of 14.5 GHz, respectively. The fabricated V-band sub-harmonic mixer has a lower conversion loss characteristics compared with ever reported mixers for millimeter frequencies.     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18 μm CMOS process to test the topology with a prototype global interconnect having a length of 10 mm. Power consumption of the transceiver for a data rate of 2.5 Gbps data is 2 mW. This gives an energy efficiency of 0.8 pJ/b.     

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4 GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0 dB improvement of single-side band noise figure, about 2.9 dB power conversion gain improvement, and 25 dB image suppression compared to those without the filter dissipating 4 mA from a 2.5 V supply voltage.     

Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.     

An ultra low power QPSK receiver based on super-regenerative oscillator with a novel digital phase detection technique

An original proposal of using SRO-based receiver to demodulate QPSK signals is presented. The receiver is composed of an LNA and a super-regenerative oscillator (SRO), both combined in a single stacked configuration for current reuse. The demodulation of received RF signal is performed via a novel digital circuit capable of detecting phase information embedded in the SRO output. The receiver is able to demodulate incoming signal without the need of an LO, PLL or an ADC. The complete receiver was designed using a 0.13 μm technology and pre-layout simulation confirms proper and efficient operation, where the designed receiver operating in the 402–405 MHz MICS band shows 135 μW power consumption, while being able to properly detect and extract sent information of a −80 dBm, 2 Mbps signal.     

Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology,including a transmitter,receiver,and fractional synthesizer.The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology,which are energy-and hardware-efficient,to enhance the data rate for a given spectrum.A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption.For the receiver,a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied.The LNA adopts a CCC boost common-gate amplifier as the input stage,and its current is reused for the second stage to save power.The mixer uses a shared amplification stage for the following passive IQ mixer.Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design.The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver,respectively.The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.     

On the use of body biasing to improve linearity in low LO-power CMOS active mixers

In a radio-frequency (RF) transceiver, the linearity of the mixer has a profound effect on the overall transceiver performance. In many RF transceivers, active mixers are used due to their higher gain which also improves the overall receiver noise figure. In a typical RF active mixer where the transistors in the LO stage switch abruptly, most of the nonlinear distortions come from the transconductance or RF stage and thus the linearity of the mixer can be enhanced by proper design of the RF stage. In low-power receivers, however, to reduce the power consumption of the local oscillator (LO) circuit, the amplitude of LO signal is low and thus the switching of the transistors in the LO stage of the mixer is gradual. In this paper, we propose a technique to improve the linearity of such low-power mixers by enhancing the linearity of the LO stage. In particular, body biasing is utilized in the LO stage to improve the linearity. To verify the effectiveness of the proposed technique, two proof-of-concept double-balanced down-conversion active mixers have been designed and fabricated in 0.13-µm CMOS. The maximum IIP3 of +2.7 dBm and −4.9 dBm at a conversion gain of 13 dB and 16 dB are achieved for the first and second prototype respectively. For a 2.4 GHz RF input signal and an intermediate-Frequency (IF) of 50 MHz, the first prototype consumes 2.4 mW from a 1.2 V supply while the second one consumes only 780 µW from a 0.7 V supply.     

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.     

Low-power highly linear UWB CMOS mixer with simultaneous second- and third-order distortion cancellation

A 3.1-4.8 GHz mode-1 UWB CMOS mixer that utilizes simultaneous second- and third-order distortion cancellation is presented. The scheme is based on a new derivative superposition, employing PMOS as an auxiliary FET to cancel the second- and the third-order nonlinear currents of common-source transconductance in the mixer and gives rise to low-distortion operation for a broad range of gate-source voltage. Full Volterra series analysis of the proposed transconductance is reported to examine the effectiveness of the new technique. Simulations in a 0.13 μm CMOS technology demonstrate that IIP3 and IIP2 of the proposed mixer have 18 and 10 dB improvements, respectively, compared with conventional Gilbert-type mixer with the same power consumption. The robustness of the technique has been verified by Monte Carlo analysis. The mixer has a gain of 12 dB and noise figure of 13 dB, while drawing only 2.5 mA from 1.2 V supply voltage.     

A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor

In this paper, a low flicker-noise, 2.4 GHz direct onversion receiver (DCR) has been designed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor in the mixing stage. The tuning inductor has been replaced by a differential active inductor circuit, which gives the same inductance, with less chip size and high quality factor. The DCR has been designed in a TSMC 0.18 μm 1P6M CMOS process for wireless LAN 802.11g applications. The proposed DCR achieves 6.7 dB SSB-NF, 34 dB conversion gain, −13.5 dBm IIP3, and flicker noise (1/f) corner frequency of 30 kHz with 137.5 mW power consumption from 1.8 V supply voltage.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-μm CMOS technology

This paper presents a wideband mixer chip covering the frequency range from 3.4 to 6.8 GHz using TSMC 0.18 μm CMOS technology. The linearity can be improved using multiple-gated-transistors (MGTR) topology. The measured 3-dB RF frequency bandwidth is from 3.1 to 6.8 GHz with an IF of 10 MHz. The measured results of the proposed mixer achieve 7.2-4.3 dB power conversion gain and 2-3 dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW, and the excellent LO-RF isolation achieved up to 54 dB at 5 GHz. The paper presents a mixer topology that is very suitable for low-power in ultra-wideband system applications.     

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18 μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7 μs and the maximum undershoot and overshoot are as low as 55 mV and 30 mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37 mV/V and 2 μV/mA, respectively.     

A dual front-end for the new GPS/GALILEO generation in a 0.35 μm SiGe process

A highly integrated, low-power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 μm SiGe process. First an analysis of the current and future GPS and GALILEO signals is presented in order to show the interoperability between both systems and to set the requirements for the entire front-end. The receiver has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4.092 MHz after digitalization. The ESD protected RF front-end exhibits a voltage gain of 103 dB and an SSB noise figure of 3.7 dB, which makes it suitable for high-sensitivity applications. The achieved power consumption is only 66 mW from a 3 V voltage supply and 38 mW if the internal dual-gain LNA is switched off with no compromise with performance and with a minimal amount of external components.     

Compact low-power implementation for continuous-time ΣΔ modulators

This paper presents a low-area continuous time (CT) sigma–delta (ΣΔ) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT ΣΔ modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25 kHz signal bandwidth with 7 μW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35 μW. A Figure Of Merit (FOM) of 0.267 pJ/state has been achieved with a total area consumption (without pads) of 110 μm×125 μm in a 0.35 μm CMOS technology.     

High efficiency boost converter with variable output voltage using a self-reference comparator

This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the V_dd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%.     

Simple and efficient inductive telemetry system with data and power transmission

This paper presents an inductive telemetry system useful for isolated applications that have to be powered and/or controlled from outside. The transmitter is based on a Class-E amplifier with ASK modulation generated with a resonant modulation to obtain the different levels to transmit. In the receiver two possible configurations, parallel and serial, are studied and the serial configuration is proposed to reduce the effect of the rectifier and the filter over the received signal. Also an ASK demodulator is fabricated in an ASIC. All the system (transmitter-receiver) has been tested and a 60% of efficiency in power transmission is obtained at a distance of 10 mm. For the data link a bit rate 1 Mbps with a carrier of 8 MHz at a distance of 20 mm has been obtained.     

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8 GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.