用于315/433MHz超再生接收机的射频前端关键技术

采用0.5μm CMOS工艺实现了用于315/433MHz超再生无线接收机的射频前端电路,包括射频放大器和超再生振荡器。文中提出了一种改进型有源电感,提高了射频放大器中谐振回路的品质因数。阐述了振荡器的自偏置效应以及振荡器输出信号幅度和电流源的关系,在此基础上实现了适用于包络检波的差分结构超再生振荡器。测试结果显示,电源电压范围为2.5V~5V,电流小于2.5mA,系统接收灵敏度优于-90dBm。     

An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of −19.7 dBm to obtain a bit-error rate (BER) of 10⁻¹². The complete receiver consumes a total power of approximately 155 mW from a 3.3-V supply. The core circuit area is 0.85×1.32 mm².     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。     

基于MAX7033的315MHz/433 MHz ASK超外差式接收电路设计

所设计的315 MHz/433 MHz ASK超外差式接收机电路采用MAX7033高集成度、低功耗CMOS、超外差式幅移键控(ASK)接收机,接收频率范围为300MHz～450 MHz,射频信号输入范围为-114 dBm～0 dBm,数据速率可达33 kb/s曼彻斯特码率(66 kb/s NRZ).介绍了MAX7033的主要技术性能、内部结构、工作原理和应用电路.     

433 MHz ASK接收机射频前端版图设计

设计了一款433 MHz ASK接收器射频前端电路(包括低噪声放大器和混频器)的版图。射频段电路对寄生效应特别敏感,设计对版图的复杂程度、面积以及由版图造成的寄生进行折中,最大程度地降低寄生对电路的影响。针对低噪声放大器电路对噪声以及混频器电路对于对称性的高要求,着重阐述了设计中对噪声的处理和实现对称性的方法。采用UMC 0.18μm工艺库进行设计和流片。将后仿真及流片测试结果与前仿真结果进行对比,得出该设计能够较好地维持原电路性能,满足系统设计要求。     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

433MHz ASK接收机中低噪声放大器的设计

采用UMC 0.18 μm 标准CMOS工艺设计了一款433 MHz ASK接收机中的LNA电路,采用差分带源极负反馈的共源共栅结构,实现单输入双输出,与混频器级联时,避免了使用外接平衡转换器.测试结果表明,该放大器的噪声系数为1.65 dB,增益则达到了18.2 dB,因此将很大程度上提高了整个接收机的噪声性能.同时输入输出匹配分别达到了-28 dB和-24 dB,IIP3也达到了-9.8 dBm,在1.8 V 的电源电压下,功耗为6.5 mW.芯片的尺寸为0.6 mm×0.9 mm.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

一种基于超再生原理的直扩通信系统新型接收机的设计

在短距离窄带无线通信系统中,具有结构简单、低成本、低功耗和灵敏度较高(相对于再生接收机)等优点的超再生接收机已经有几十年的应用历史。这里,根据超再生的基本原理,构建出一种用于对直序列扩频(DS-SS)信号进行非相干检测的扩频接收机的新型结构,并对其在2.4GHz的ISM波段的宽带应用进行分析。     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

Path loss prediction in microcellular environments at 900 MHz

A model is proposed to estimate path loss in urban environments at 900 MHz when the base station antenna is below the average height of the buildings. It shows that the percentage of area occupied by buildings explains more than 20 dB of variation of the mean path loss.     

Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature (T < 180 °C)

The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180 °C, is shown to lead to a very efficient control of the threshold voltage V_TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of V_TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50 nm thick, active layer and to its electrical quality that leads to a full depletion.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

智能家居433 MHz射频通信协议栈设计与网关实现

摘要：针对智能家居内部网络低成本、短距离、低数据速率的通信与组网需求,设计了一种基于CC1101的433 MHz射频通信协议栈,并实现了以嵌入式操作系统μC/OS-II与微控制器STM32F407为基础的智能网关。该智能网关搭载Wi-Fi、GSM、网卡等功能模块,与433 MHz 射频通信协议栈协调工作实现了多种智能控制方式。详细介绍了433 MHz射频协议栈设计、通信协议与节点模型的定义、433 MHz射频网络组建、数据冲突退避与重发机制。该方案具有简单实用的特点,适合家庭内部网络使用。     

An Inductorless 300 MHz Wideband CMOS Power Amplifier

The power amplifier tends to be one of the most demanding parts to fully integrate when building an entire radio on a CMOS chip. In this paper the design of a fully integrated RF power amplifier without inductors is described. As inductors in CMOS technology are associated with various problems, it is interesting to examine what performance can be achieved without them. An amplifier with an operating band from 60 MHz to 300 MHz (–3 dB) is built in 0.8 m CMOS. A 3 V supply is used. The measured midband power gain is 30 dB with 50 resistive source and load impedance. As linearity is important for many modern modulation schemes, the amplifier is designed to be as linear as possible. The measured third order intercept point is 23 dBm and the 1 dB compression point is 10 dBm, both referred to the output. The output is single ended to avoid an off-chip differential to single ended transformer.