Temperature dependence of the interface state distribution due to hot carrier effect in FinFET device

Temperature dependence of the interface state distribution due to hot carrier injection (HCI) effect in FinFET device is investigated in this paper. The interface state distribution along the FinFET channel at various temperatures is first extracted by measuring the generation-recombination (G-R) current and then the shift of interface state density with temperature is analyzed. The result shows that the density of interface states increases with elevating temperature from 28 °C to 128 °C. While the change of generation rate slows down with rising temperature and the distribution region is insensitive to both stress time and temperature. Based on the measured data, an empirical Gaussian-like model is proposed to describe the interface state distribution along the FinFET channel and good agreements with experimental data are obtained.     

S-parameter performance degradation in power RF N-LDMOS devices due to hot carrier effects

This paper reports comparative study of technology reliability after accelerated ageing tests under various conditions (electrical and/or thermal stress) and RF life-tests reliability with pulsed bench for radar applications in S-band. It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters.The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS–SILVACO simulations.S-parameters degradation of hot-carrier stressed n-MOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO₂ interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. From our experimental results, hot electron induced RF performance degradation should be taken into consideration in the design of the power RF MOS devices.     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

An empirical model for device degradation due to hot-carrier injection

An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a Vthshift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.     

Process dependence of interface state generation due to irradiation and hot carrier stress in rapid thermally nitrided thin gate oxides

A study of the effects of nitridation time and temperature on the interface state generation in MOS devices with thin rapid thermally nitrided gate oxides is reported. A different process dependence was observed for interface state generation caused by X-ray irradiation and hot carrier stress. The discrepancy is explained using the structural changes at the interface during nitridation and some of the earlier defect generation models.<>     

Study of performance degradations in DC-DC converter due to hot carrier stress by simulation

The hot carrier effects on the 0.25 μm high voltage LDMOS has been examined by the accelerated stress experiment. Although the model parameters changed slightly, the switching performances degraded significantly, which have been simulated with the compact models extracted from the test devices by ICCAP. A full bridge DC-DC converter with the compact models was proposed in Cadence SpectreRF. The simulated results show that the efficiency of the full bridge DC-DC converter degraded significantly due to the hot carrier effects.     

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

Spatial distribution of hot electrons as a physical limit to MOS transistor performance

The spatial distribution of the free carriers in the channel of a MOS transistor is changed in the hot-electron regime. There the electron distance from the oxide is enlarged, causing a reduction of gate capacitance and transistor current. This is a physical limit to the performance of MOSFETs with short channels and thin gate oxides.     

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications

Channel hot carrier (CHC) degradation is one of the major reliability concerns for nanoscale transistors. To simulate the impact of CHC on analog circuits, a unified analytical model able to cope with various design and process parameters is proposed. In addition, our model can handle initial degradation and varying stress conditions, allowing the designer to estimate the impact of CHC on transistor performance for arbitrary stressing patterns. The model is experimentally verified in a 65 nm CMOS technology. Expressions to simulate the impact of transistor degradation on relevant transistor parameters like output conductance and threshold voltage degradation are presented and verified.     

A transformed analytical model for thermal noise of FinFET based on fringing field approximation

This paper delineates the effect of nonplanar structure of FinFETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended (underlap) S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional (3-D) structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 dB and 100 Ω respectively and optimum admittance increases to 5.45 mω at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.     

Approximation of SNR degradation due to carrier frequency offset for OFDM in shadowed multipath channels

We derive an approximate expression for signal-to-noise ratio (SNR) degradation of orthogonal frequency division multiplexing due to carrier frequency offset over a shadowed multipath channel, to explicitly show the effects of system and channel parameters on the degradation of the received SNR. The results show that, for small frequency offset, the SNR degradation is proportional to the square of the frequency offset and the square of the number of subcarriers. It is also shown that, if E/sub s//N/sub 0/ is reasonably large, the SNR degradation becomes insensitive to E/sub s//N/sub 0/, which is contrary to the case of the additive white Gaussian noise channel.     

A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon

A theoretical model that describes the dependence of carrier lifetime on doping density, which is based on the equilibrium solubility of a single defect in nondegenerately doped silicon, is developed. The model predictions are consistent with the longest measured hole and electron lifetimes reported for n-type and p-type silicon, and hence imply a possibly “fundamental” (unavoidable) defect in silicon. The defect is acceptor-type and is more soluble in n-type than in p-type silicon, which suggests a longer fundamental limit for electron lifetime than for hole lifetime at a given nondegenerate doping density. The prevalent, minimum density of the defect, which defines these limits, occurs at the processing temperature below which the defect is virtually immobile in the silicon lattice. The analysis reveals that this temperature is in the range 300–400°C, and thus emphasizes, when related also to common non-fundamental defects, the significance of low-temperature processing in the fabrication of silicon devices requiring long or well-controlled carrier lifetimes.     

A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors

This paper reports the early stage of dc hot carrier degradation behaviour of n-channel low doped drain metal oxide semiconductor field effect transistors in a range of deep sub-micron technologies. A deviation from the normally observed power-law expression tⁿ at short time scales is revealed. In addition, under V_G=V_D condition, anomalous behaviour characterised by a saturation in the transconductance degradation prior to the power-law regime is observed. The factors contributing to the damage evolution are analysed by extraction of the parasitic source–drain series resistance and the effective mobility. Depending on the voltage rating of the technology, the relative contributions of these two underlying causes, at various times, to the total degradation are different. For the 5 V technologies, both the series resistance and the mobility play significant roles, with the early stage dominated by an increase in series resistance. On the other hand, the series resistance has a negligible influence relative to the mobility on the degradation mechanism of the 3 V technologies.     

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A statistical model to predict grain boundary distribution in the channel of a polysilicon thin-film transistor (TFT) is proposed. The model is valid for arbitrary transistor size to grain size ratio, and is particularly useful to predict the grain boundary distribution of recrystallized large-grain polysilicon TFTs where the transistor size is comparable to the grain size and gives significant device-to-device variation. The model has been extensively verified by comparing it with statistical data obtained from TFTs fabricated using metal-induced-lateral-crystallization and regular solid-phase epitaxial techniques. Good agreements between the experimental results and model prediction are demonstrated.     

Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling

This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular, the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved converters in the presence of substrate noise.     

A two-dimensional electrostatic model for degraded LDD-nMOSFETs including spatial and energy distribution of hot-carrier-induced interface traps

A two-dimensional electrostatic model for degraded short channel lightly doped drain (LDD)-nMOSFETs is presented. The model is based on a numerical solution of the Poisson equation using the five-point finite difference approximation. The model takes into account all device details including doping profiles and spatial and energy distribution of hot-carrier induced interface traps in the LDD region. Potential and charge distributions within the device in weak (subthreshold) and strong inversion regimes have been extensively studied. The validation of the model has been carried out through comparison between simulated I-V characteristics in the linear region and published experimental data. The results obtained have shown that the drain current is greatly affected by the energy distribution of interface traps, especially in the low gate voltage range (near-threshold and subthreshold).     

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.     

A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit.     

A simplified model based on clearness index for estimating yearly performance of hybrid PV energy systems

A simplified model for estimating the energy contribution of PV converter in a hybrid PV–wind system is presented. The simplified model determines the yearly solar fraction, that is the fraction of energy demand provided by PV, and the remaining loss of load (LOL) is assumed to be provided by wind turbines. The novel model is based on simulation results derived from 8 years of measured hour‐by‐hour solar irradiation data from five different locations in the world. The system performance is simulated by the PV–wind energy simulation program of the Cardiff School of Engineering (ARES). An hourly constant load profile is assumed. The performance of a PV system is primarily dependent on the solar irradiation distribution in a given location for the period of time in question. The new model correlates the location dependence observed in the yearly solar fraction curves of different data sets with one of the most characteristic solar irradiation distribution parameters, the yearly clearness index of the respective solar irradiation data. The new model requires the yearly clearness index value, which is commonly available for most locations throughout the world, as input. As the novel model is validated with solar irradiation data from different locations in the world, it could be used for predicting the solar fraction in a hybrid PV system with a very high level of accuracy, for a wide range of climates. Copyright © 2002 John Wiley & Sons, Ltd.